src/soc/intel/common/block/lpc/lpc_def.h

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #ifndef _SOC_COMMON_BLOCK_LPC_DEF_H_
   5 #define _SOC_COMMON_BLOCK_LPC_DEF_H_
   6
   7 #define LPC_SERIRQ_CTL                  0x64
   8 #define  LPC_SCNT_EN                    (1 << 7)
   9 #define  LPC_SCNT_MODE                  (1 << 6)
  10 #define LPC_IO_DECODE                   0x80
  11 #define  LPC_IOD_COMA_RANGE             (0 << 0) /* 0x3F8 - 0x3FF COMA*/
  12 #define  LPC_IOD_COMB_RANGE             (1 << 4) /* 0x2F8 - 0x2FF COMB*/
  13 /* Use IO_<peripheral>_<IO port> style macros defined in lpc_lib.h
  14  * to enable decoding of I/O locations for a peripheral. */
  15 #define LPC_IO_ENABLES                  0x82
  16 #define LPC_GENERIC_IO_RANGE(n)         ((((n) & 0x3) * 4) + 0x84)
  17 #define  LPC_LGIR_AMASK_MASK            (0xfc << 16)
  18 #define  LPC_LGIR_ADDR_MASK             0xfffc
  19 #define  LPC_LGIR_EN                    (1 << 0)
  20 #define LPC_LGIR_MAX_WINDOW_SIZE        256
  21 #define LPC_GENERIC_MEM_RANGE           0x98
  22 #define  LPC_LGMR_ADDR_MASK             0xffff0000
  23 #define  LPC_LGMR_EN                    (1 << 0)
  24 #define LPC_LGMR_WINDOW_SIZE            (64 * KiB)
  25 #define LPC_BIOS_CNTL                   0xdc
  26 #define  LPC_BC_BILD                    (1 << 7) /* BILD */
  27 #define  LPC_BC_LE                      (1 << 1) /* LE */
  28 #define  LPC_BC_EISS                    (1 << 5) /* EISS */
  29 #define LPC_PCCTL                       0xE0 /* PCI Clock Control */
  30 #define  LPC_PCCTL_CLKRUN_EN            (1 << 0)
  31
  32 #endif /* _SOC_COMMON_BLOCK_LPC_DEF_H_ */