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treewide: replace GPLv2 long form headers with SPDX header
[coreboot.git] / src / soc / intel / common / block / include / intelblocks / gpio_defs.h
blob266d093868ba67f0daa647b2e50f55c1e49dfc26
1 /* This file is part of the coreboot project. */
2 /* SPDX-License-Identifier: GPL-2.0-or-later */
3
4 #ifndef _SOC_BLOCK_GPIO_DEFS_H_
5 #define _SOC_BLOCK_GPIO_DEFS_H_
6
7 #define PAD_CFG0_TX_STATE_BIT 0
8 #define PAD_CFG0_TX_STATE (1 << PAD_CFG0_TX_STATE_BIT)
9 #define PAD_CFG0_RX_STATE_BIT 1
10 #define PAD_CFG0_RX_STATE (1 << PAD_CFG0_RX_STATE_BIT)
11 #define PAD_CFG0_TX_DISABLE (1 << 8)
12 #define PAD_CFG0_RX_DISABLE (1 << 9)
13 #define PAD_CFG0_MODE_SHIFT 10
14 #define PAD_CFG0_MODE_MASK (7 << 10)
15 #define PAD_CFG0_MODE_GPIO (0 << 10)
16 #define PAD_CFG0_MODE_FUNC(x) ((x) << 10)
17 #define PAD_CFG0_MODE_NF1 (1 << 10)
18 #define PAD_CFG0_MODE_NF2 (2 << 10)
19 #define PAD_CFG0_MODE_NF3 (3 << 10)
20 #define PAD_CFG0_MODE_NF4 (4 << 10)
21 #define PAD_CFG0_MODE_NF5 (5 << 10)
22 #define PAD_CFG0_MODE_NF6 (6 << 10)
23 #define PAD_CFG0_MODE_NF7 (7 << 10)
24 #define PAD_CFG0_ROUTE_MASK (0xF << 17)
25 #define PAD_CFG0_ROUTE_NMI (1 << 17)
26 #define PAD_CFG0_ROUTE_SMI (1 << 18)
27 #define PAD_CFG0_ROUTE_SCI (1 << 19)
28 #define PAD_CFG0_ROUTE_IOAPIC (1 << 20)
29 #define PAD_CFG0_RXTENCFG_MASK (3 << 21)
30 #define PAD_CFG0_RXINV_MASK (1 << 23)
31 #define PAD_CFG0_RX_POL_INVERT (1 << 23)
32 #define PAD_CFG0_RX_POL_NONE (0 << 23)
33 #define PAD_CFG0_PREGFRXSEL (1 << 24)
34 #define PAD_CFG0_TRIG_MASK (3 << 25)
35 #define PAD_CFG0_TRIG_LEVEL (0 << 25)
36 #define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/
37 #define PAD_CFG0_TRIG_OFF (2 << 25)
38 #define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25)
39 #define PAD_CFG0_RXRAW1_MASK (1 << 28)
40 #define PAD_CFG0_RXPADSTSEL_MASK (1 << 29)
41 #define PAD_CFG0_RESET_MASK (3 << 30)
42 #define PAD_CFG0_LOGICAL_RESET_PWROK (0U << 30)
43 #define PAD_CFG0_LOGICAL_RESET_DEEP (1U << 30)
44 #define PAD_CFG0_LOGICAL_RESET_PLTRST (2U << 30)
45 #define PAD_CFG0_LOGICAL_RESET_RSMRST (3U << 30)
46
47 /*
48 * Use the fourth bit in IntSel field to indicate gpio
49 * ownership. This field is RO and hence not used during
50 * gpio configuration.
51 */
52 #define PAD_CFG_OWN_GPIO_DRIVER (1 << 4)
53 #define PAD_CFG_OWN_GPIO_ACPI (0 << 4)
54 #define PAD_CFG_OWN_GPIO(own) PAD_CFG_OWN_GPIO_##own
55
56 #define PAD_CFG1_IRQ_MASK (0xff << 0)
57 #define PAD_CFG1_IOSTERM_MASK (0x3 << 8)
58 #define PAD_CFG1_IOSTERM_SAME (0x0 << 8)
59 #define PAD_CFG1_IOSTERM_DISPUPD (0x1 << 8)
60 #define PAD_CFG1_IOSTERM_ENPD (0x2 << 8)
61 #define PAD_CFG1_IOSTERM_ENPU (0x3 << 8)
62 #define PAD_CFG1_PULL_MASK (0xf << 10)
63 #define PAD_CFG1_PULL_NONE (0x0 << 10)
64 #define PAD_CFG1_PULL_DN_5K (0x2 << 10)
65 #define PAD_CFG1_PULL_DN_20K (0x4 << 10)
66 #define PAD_CFG1_PULL_UP_1K (0x9 << 10)
67 #define PAD_CFG1_PULL_UP_5K (0xa << 10)
68 #define PAD_CFG1_PULL_UP_2K (0xb << 10)
69 #define PAD_CFG1_PULL_UP_20K (0xc << 10)
70 #define PAD_CFG1_PULL_UP_667 (0xd << 10)
71 #define PAD_CFG1_PULL_NATIVE (0xf << 10)
72 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY)
73 /* Tx enabled driving last value driven, Rx enabled */
74 #define PAD_CFG1_IOSSTATE_TxLASTRxE (0x0 << 14)
75 /* Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller
76 * internally */
77 #define PAD_CFG1_IOSSTATE_Tx0RxDCRx0 (0x1 << 14)
78 /* Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller
79 * internally */
80 #define PAD_CFG1_IOSSTATE_Tx0RxDCRx1 (0x2 << 14)
81 /* Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller
82 * internally */
83 #define PAD_CFG1_IOSSTATE_Tx1RxDCRx0 (0x3 << 14)
84 /* Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller
85 * internally */
86 #define PAD_CFG1_IOSSTATE_Tx1RxDCRx1 (0x4 << 14)
87 /* Tx enabled driving 0, Rx enabled */
88 #define PAD_CFG1_IOSSTATE_Tx0RxE (0x5 << 14)
89 /* Tx enabled driving 1, Rx enabled */
90 #define PAD_CFG1_IOSSTATE_Tx1RxE (0x6 << 14)
91 /* Hi-Z, Rx driving 0 back to its controller internally */
92 #define PAD_CFG1_IOSSTATE_HIZCRx0 (0x7 << 14)
93 /* Hi-Z, Rx driving 1 back to its controller internally */
94 #define PAD_CFG1_IOSSTATE_HIZCRx1 (0x8 << 14)
95 #define PAD_CFG1_IOSSTATE_TxDRxE (0x9 << 14) /* Tx disabled, Rx enabled */
96 #define PAD_CFG1_IOSSTATE_IGNORE (0xf << 14) /* Ignore Iostandby */
97 #define PAD_CFG1_IOSSTATE_MASK (0xf << 14) /* mask to extract Iostandby bits */
98 #define PAD_CFG1_IOSSTATE_SHIFT 14 /* set Iostandby bits [17:14] */
99 #else /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY */
100 #define PAD_CFG1_IOSSTATE_MASK 0
101 #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY */
102
103 #define PAD_CFG2_DEBEN 1
104 /* Debounce Duration = (2 ^ PAD_CFG2_DEBOUNCE_x_RTC) * RTC clock duration */
105 #define PAD_CFG2_DEBOUNCE_8_RTC (0x3 << 1)
106 #define PAD_CFG2_DEBOUNCE_16_RTC (0x4 << 1)
107 #define PAD_CFG2_DEBOUNCE_32_RTC (0x5 << 1)
108 #define PAD_CFG2_DEBOUNCE_64_RTC (0x6 << 1)
109 #define PAD_CFG2_DEBOUNCE_128_RTC (0x7 << 1)
110 #define PAD_CFG2_DEBOUNCE_256_RTC (0x8 << 1)
111 #define PAD_CFG2_DEBOUNCE_512_RTC (0x9 << 1)
112 #define PAD_CFG2_DEBOUNCE_1K_RTC (0xa << 1)
113 #define PAD_CFG2_DEBOUNCE_2K_RTC (0xb << 1)
114 #define PAD_CFG2_DEBOUNCE_4K_RTC (0xc << 1)
115 #define PAD_CFG2_DEBOUNCE_8K_RTC (0xd << 1)
116 #define PAD_CFG2_DEBOUNCE_16K_RTC (0xe << 1)
117 #define PAD_CFG2_DEBOUNCE_32K_RTC (0xf << 1)
118 #define PAD_CFG2_DEBOUNCE_MASK 0x1f
119
120 /* voltage tolerance 0=3.3V default 1=1.8V tolerant */
121 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
122 #define PAD_CFG1_TOL_MASK (0x1 << 25)
123 #define PAD_CFG1_TOL_1V8 (0x1 << 25)
124 #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL */
125
126 #define PAD_FUNC(value) PAD_CFG0_MODE_##value
127 #define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value
128 #define PAD_PULL(value) PAD_CFG1_PULL_##value
129
130 /* Disable the input/output buffer of the pad */
131 #define PAD_CFG0_BUF_NO_DISABLE (0)
132 #define PAD_CFG0_BUF_TX_DISABLE PAD_CFG0_TX_DISABLE
133 #define PAD_CFG0_BUF_RX_DISABLE PAD_CFG0_RX_DISABLE
134 #define PAD_CFG0_BUF_TX_RX_DISABLE \
135 (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE)
136
137 #define PAD_BUF(value) PAD_CFG0_BUF_##value
138
139 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY)
140 #define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value
141 #define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value
142 #else
143 #define PAD_IOSSTATE(value) 0
144 #define PAD_IOSTERM(value) 0
145 #endif
146
147 #define PAD_IRQ_CFG(route, trig, inv) \
148 (PAD_CFG0_ROUTE_##route | \
149 PAD_CFG0_TRIG_##trig | \
150 PAD_CFG0_RX_POL_##inv)
151
152 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT)
153 #define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \
154 (PAD_CFG0_ROUTE_##route1 | \
155 PAD_CFG0_ROUTE_##route2 | \
156 PAD_CFG0_TRIG_##trig | \
157 PAD_CFG0_RX_POL_##inv)
158 #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */
159
160 #define _PAD_CFG_STRUCT(__pad, __config0, __config1) \
161 { \
162 .pad = __pad, \
163 .pad_config[0] = __config0, \
164 .pad_config[1] = __config1, \
165 }
166
167 #if GPIO_NUM_PAD_CFG_REGS > 2
168 #define _PAD_CFG_STRUCT_3(__pad, __config0, __config1, __config2) \
169 { \
170 .pad = __pad, \
171 .pad_config[0] = __config0, \
172 .pad_config[1] = __config1, \
173 .pad_config[2] = __config2, \
174 }
175 #else
176 #define _PAD_CFG_STRUCT_3(__pad, __config0, __config1, __config2) \
177 _PAD_CFG_STRUCT(__pad, __config0, __config1)
178 #endif
179
180 /* Native function configuration */
181 #define PAD_CFG_NF(pad, pull, rst, func) \
182 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
183 PAD_IOSSTATE(TxLASTRxE))
184
185 /*
186 * Set native function with RX Level/Edge configuration and disable
187 * input/output buffer if necessary
188 */
189 #define PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) \
190 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_CFG0_TRIG_##trig | \
191 PAD_BUF(bufdis) | PAD_FUNC(func), \
192 PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
193
194 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
195 /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S
196 Not applicable to all SOCs. Refer EDS
197 */
198 #define PAD_CFG_NF_1V8(pad, pull, rst, func) \
199 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) |\
200 PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_TOL_1V8)
201 #endif
202
203 /* Native function configuration for standby state */
204 #define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \
205 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
206 PAD_IOSSTATE(iosstate))
207
208 /* Native function configuration for standby state, also configuring
209 iostandby as masked */
210 #define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \
211 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
212 PAD_IOSSTATE(IGNORE))
213
214 /* Native function configuration for standby state, also configuring
215 iosstate and iosterm */
216 #define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \
217 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
218 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
219
220 /* Configure native function, iosstate, iosterm and disable input/output buffer */
221 #define PAD_CFG_NF_BUF_IOSSTATE_IOSTERM(pad, pull, rst, func, bufdis, iosstate, iosterm) \
222 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_BUF(bufdis) | PAD_FUNC(func), \
223 PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
224
225 /* General purpose output, no pullup/down. */
226 #define PAD_CFG_GPO(pad, val, rst) \
227 _PAD_CFG_STRUCT(pad, \
228 PAD_FUNC(GPIO) | PAD_RESET(rst) | \
229 PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \
230 PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE))
231
232 /* General purpose output, with termination specified */
233 #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \
234 _PAD_CFG_STRUCT(pad, \
235 PAD_FUNC(GPIO) | PAD_RESET(rst) | \
236 PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \
237 PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
238
239 /* General purpose output, no pullup/down. */
240 #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \
241 _PAD_CFG_STRUCT(pad, \
242 PAD_FUNC(GPIO) | PAD_RESET(rst) | \
243 PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \
244 PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG_OWN_GPIO(DRIVER))
245
246 /* General purpose output. */
247 #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \
248 _PAD_CFG_STRUCT(pad, \
249 PAD_FUNC(GPIO) | PAD_RESET(rst) | \
250 PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \
251 PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm))
252
253 /* General purpose input */
254 #define PAD_CFG_GPI(pad, pull, rst) \
255 _PAD_CFG_STRUCT(pad, \
256 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \
257 PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
258
259 #define PAD_CFG_GPI_IOSSTATE(pad, pull, rst, iosstate) \
260 _PAD_CFG_STRUCT(pad, \
261 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
262 PAD_PULL(pull) | PAD_IOSSTATE(iosstate))
263
264 #define PAD_CFG_GPI_IOSSTATE_IOSTERM(pad, pull, rst, iosstate, iosterm) \
265 _PAD_CFG_STRUCT(pad, \
266 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
267 PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
268
269 /*
270 * General purpose input. The following macro sets the
271 * Host Software Pad Ownership to GPIO Driver mode.
272 */
273 #define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) \
274 _PAD_CFG_STRUCT(pad, PAD_FUNC(GPIO) | PAD_RESET(rst) | \
275 PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE), \
276 PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE) | PAD_CFG_OWN_GPIO(own))
277
278 #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \
279 _PAD_CFG_STRUCT(pad, \
280 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \
281 PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | PAD_IOSSTATE(TxDRxE))
282
283 #define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \
284 _PAD_CFG_STRUCT(pad, \
285 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \
286 PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | \
287 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
288
289 #define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \
290 _PAD_CFG_STRUCT(pad, \
291 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \
292 PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
293
294 /* GPIO Interrupt */
295 #define PAD_CFG_GPI_INT(pad, pull, rst, trig) \
296 PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, DRIVER)
297
298 /*
299 * No Connect configuration for unused pad.
300 * Both TX and RX are disabled. RX disabling is done to avoid unnecessary
301 * setting of GPI_STS. RX Level/Edge Trig Configuration set to disable
302 */
303 #define PAD_NC(pad, pull) \
304 _PAD_CFG_STRUCT(pad, \
305 PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \
306 PAD_CFG0_TRIG_OFF | PAD_BUF(TX_RX_DISABLE), \
307 PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
308
309 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS)
310
311 #define PAD_CFG_GPI_APIC(pad, pull, rst) \
312 _PAD_CFG_STRUCT(pad, \
313 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
314 PAD_IRQ_CFG(IOAPIC, LEVEL, NONE), PAD_PULL(pull))
315
316 #define PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) \
317 _PAD_CFG_STRUCT(pad, \
318 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
319 PAD_IRQ_CFG(IOAPIC, LEVEL, INVERT), PAD_PULL(pull))
320
321 #define PAD_CFG_GPI_ACPI_SCI(pad, pull, rst, inv) \
322 PAD_CFG_GPI_SCI(pad, pull, rst, EDGE_SINGLE, inv)
323
324 #define PAD_CFG_GPI_ACPI_SMI(pad, pull, rst, inv) \
325 PAD_CFG_GPI_SMI(pad, pull, rst, EDGE_SINGLE, inv)
326
327 #define PAD_CFG_NC(pad) PAD_NC(pad, NONE)
328
329 #define PAD_CFG1_PULL_20K_PU PAD_CFG1_PULL_UP_20K
330 #define PAD_CFG1_PULL_5K_PU PAD_CFG1_PULL_UP_5K
331 #define PAD_CFG1_PULL_20K_PD PAD_CFG1_PULL_DN_20K
332 #define PAD_CFG0_TRIG_EDGE PAD_CFG0_TRIG_EDGE_SINGLE
333 #define PAD_CFG0_RX_POL_YES PAD_CFG0_RX_POL_INVERT
334
335 #else
336 /* General purpose input, routed to APIC */
337 #define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \
338 _PAD_CFG_STRUCT(pad, \
339 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
340 PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
341 PAD_IOSSTATE(TxDRxE))
342 #endif
343
344 /* General purpose input, routed to APIC - with IOStandby Config*/
345 #define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
346 _PAD_CFG_STRUCT(pad, \
347 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
348 PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
349 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
350
351 /*
352 * The following APIC macros assume the APIC will handle the filtering
353 * on its own end. One just needs to pass an active high message into the
354 * ITSS.
355 */
356 #define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \
357 PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT)
358
359 #define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \
360 PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE)
361
362 #define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \
363 PAD_CFG_GPI_APIC(pad, pull, rst, EDGE_SINGLE, INVERT)
364
365 /* General purpose input, routed to SMI */
366 #define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \
367 _PAD_CFG_STRUCT(pad, \
368 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
369 PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \
370 PAD_IOSSTATE(TxDRxE))
371
372 /* General purpose input, routed to SMI */
373 #define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
374 _PAD_CFG_STRUCT(pad, \
375 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
376 PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \
377 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
378
379 #define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \
380 PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT)
381
382 #define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \
383 PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE)
384
385 /* General purpose input, routed to SCI */
386 #define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \
387 _PAD_CFG_STRUCT(pad, \
388 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
389 PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
390 PAD_IOSSTATE(TxDRxE))
391
392 /* General purpose input, routed to SCI */
393 #define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
394 _PAD_CFG_STRUCT(pad, \
395 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
396 PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
397 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
398
399 #define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \
400 PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT)
401
402 #define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \
403 PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE)
404
405 #define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \
406 _PAD_CFG_STRUCT_3(pad, \
407 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
408 PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
409 PAD_IOSSTATE(TxDRxE), PAD_CFG2_DEBEN | PAD_CFG2_##dur)
410
411 #define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \
412 PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, INVERT, dur)
413
414 #define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \
415 PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, NONE, dur)
416
417 /* General purpose input, routed to NMI */
418 #define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \
419 _PAD_CFG_STRUCT(pad, \
420 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
421 PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \
422 PAD_IOSSTATE(TxDRxE))
423
424 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT)
425 #define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \
426 _PAD_CFG_STRUCT(pad, \
427 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
428 PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \
429 PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
430
431 #define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \
432 PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI)
433
434 #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */
435
436 #endif /* _SOC_BLOCK_GPIO_DEFS_H_ */
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