src/soc/intel/common/block/include/intelblocks/cse.h

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #ifndef SOC_INTEL_COMMON_CSE_H
   5 #define SOC_INTEL_COMMON_CSE_H
   6
   7 #include <stdint.h>
   8 #include <types.h>
   9
  10 /* MKHI Command groups */
  11 #define MKHI_GROUP_ID_CBM       0x0
  12 #define MKHI_GROUP_ID_HMRFPO    0x5
  13 #define MKHI_GROUP_ID_GEN       0xff
  14 #define MKHI_GROUP_ID_BUP_COMMON        0xf0
  15
  16 /* Global Reset Command ID */
  17 #define MKHI_CBM_GLOBAL_RESET_REQ       0xb
  18
  19 /* Origin of Global Reset command */
  20 #define GR_ORIGIN_BIOS_POST     0x2
  21
  22 /* HMRFPO Command Ids */
  23 #define MKHI_HMRFPO_ENABLE      0x1
  24 #define MKHI_HMRFPO_GET_STATUS  0x3
  25
  26 /* Get Firmware Version Command Id */
  27 #define MKHI_GEN_GET_FW_VERSION 0x2
  28
  29 /* Boot partition info and set boot partition info command ids */
  30 #define MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO 0x1c
  31 #define MKHI_BUP_COMMON_SET_BOOT_PARTITION_INFO 0x1d
  32
  33 /* ME Current Working States */
  34 #define ME_HFS1_CWS_NORMAL      0x5
  35
  36 /* ME Current Operation Modes */
  37 #define ME_HFS1_COM_NORMAL      0x0
  38 #define ME_HFS1_COM_SOFT_TEMP_DISABLE   0x3
  39 #define ME_HFS1_COM_SECOVER_MEI_MSG     0x5
  40
  41 /* ME Firmware SKU Types */
  42 #define ME_HFS3_FW_SKU_CONSUMER 0x2
  43 #define ME_HFS3_FW_SKU_CORPORATE        0x3
  44 #define ME_HFS3_FW_SKU_CUSTOM   0x5
  45
  46 /* HFSTS register offsets in PCI config space */
  47 enum {
  48         PCI_ME_HFSTS1 = 0x40,
  49         PCI_ME_HFSTS2 = 0x48,
  50         PCI_ME_HFSTS3 = 0x60,
  51         PCI_ME_HFSTS4 = 0x64,
  52         PCI_ME_HFSTS5 = 0x68,
  53         PCI_ME_HFSTS6 = 0x6C,
  54 };
  55
  56 /* MKHI Message Header */
  57 struct mkhi_hdr {
  58         uint8_t group_id;
  59         uint8_t command:7;
  60         uint8_t is_resp:1;
  61         uint8_t rsvd;
  62         uint8_t result;
  63 } __packed;
  64
  65 /* set up device for use in early boot enviroument with temp bar */
  66 void heci_init(uintptr_t bar);
  67 /*
  68  * Receive message into buff not exceeding maxlen. Message is considered
  69  * successfully received if a 'complete' indication is read from ME side
  70  * and there was enough space in the buffer to fit that message. maxlen
  71  * is updated with size of message that was received. Returns 0 on failure
  72  * and 1 on success.
  73  * In case of error heci_reset() may be requiered.
  74  */
  75 int heci_receive(void *buff, size_t *maxlen);
  76 /*
  77  * Send message msg of size len to host from host_addr to cse_addr.
  78  * Returns 1 on success and 0 otherwise.
  79  * In case of error heci_reset() may be requiered.
  80  */
  81 int
  82 heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t cse_addr);
  83
  84 /*
  85  * Sends snd_msg of size snd_sz, and reads message into buffer pointed by
  86  * rcv_msg of size rcv_sz
  87  * Returns 0 on failure and 1 on success.
  88  */
  89 int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz);
  90
  91 /*
  92  * Attempt device reset. This is useful and perhaps only thing left to do when
  93  * CPU and CSE are out of sync or CSE fails to respond.
  94  * Returns 0 on failure and 1 on success.
  95  */
  96 int heci_reset(void);
  97 /* Disable HECI using Sideband interface communication */
  98 void heci_disable(void);
  99
 100 /* Reads config value from a specified offset in the CSE PCI Config space. */
 101 uint32_t me_read_config32(int offset);
 102
 103 /*
 104  * Check if the CSE device is enabled in device tree. Also check if the device
 105  * is visible on the PCI bus by reading config space.
 106  * Return true if device present and config space enabled, else return false.
 107  */
 108 bool is_cse_enabled(void);
 109
 110 /* Makes the host ready to communicate with CSE */
 111 void cse_set_host_ready(void);
 112
 113 /*
 114  * Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds.
 115  * Returns 0 on failure and 1 on success.
 116  */
 117 uint8_t cse_wait_sec_override_mode(void);
 118
 119 enum rst_req_type {
 120         GLOBAL_RESET = 1,
 121         CSE_RESET_ONLY = 3,
 122 };
 123
 124 /*
 125  * Sends GLOBAL_RESET_REQ cmd to CSE.
 126  * The reset type can be one of the above defined reset type.
 127  * Returns 0 on failure and 1 on success.
 128  */
 129 int cse_request_global_reset(enum rst_req_type rst_type);
 130
 131 /*
 132  * Sends HMRFPO_ENABLE command.
 133  * HMRFPO - Host ME Region Flash Protection Override.
 134  * For CSE Firmware SKU Custom, procedure to place CSE in HMRFPO (SECOVER_MEI_MSG) mode:
 135  *      1. Ensure CSE boots from BP1(RO).
 136  *              - Send set_next_boot_partition(BP1)
 137  *              - Issue CSE Only Reset
 138  *      2. Send HMRFPO_ENABLE command to CSE. Further, no reset is required.
 139  *
 140  * The HMRFPO mode prevents CSE to execute SPI I/O cycles to CSE region, and unlocks
 141  * the CSE region to perform updates to it.
 142  * This command is only valid before EOP.
 143  *
 144  * Returns 0 on failure to send HECI command and to enable HMRFPO mode, and 1 on success.
 145  *
 146  */
 147 int cse_hmrfpo_enable(void);
 148
 149 /*
 150  * Send HMRFPO_GET_STATUS command.
 151  * returns -1 on failure and 0 (DISABLED)/ 1 (LOCKED)/ 2 (ENABLED)
 152  * on success.
 153  */
 154 int cse_hmrfpo_get_status(void);
 155
 156 /* Fixed Address MEI Header's Host Address field value */
 157 #define BIOS_HOST_ADDR  0x00
 158
 159 /* Fixed Address MEI Header's ME Address field value */
 160 #define HECI_MKHI_ADDR  0x07
 161
 162 /* HMRFPO Status types */
 163 /* Host can't access ME region */
 164 #define MKHI_HMRFPO_DISABLED    0
 165
 166 /*
 167  * ME Firmware locked down HMRFPO Feature.
 168  * Host can't access ME region.
 169  */
 170 #define MKHI_HMRFPO_LOCKED      1
 171
 172 /* Host can access ME region */
 173 #define MKHI_HMRFPO_ENABLED     2
 174
 175 /*
 176  * Queries and logs ME firmware version
 177  */
 178 void print_me_fw_version(void *unused);
 179
 180 /*
 181  * Checks current working operation state is normal or not.
 182  * Returns true if CSE's current working state is normal, otherwise false.
 183  */
 184 bool cse_is_hfs1_cws_normal(void);
 185
 186 /*
 187  * Checks CSE's current operation mode is normal or not.
 188  * Returns true if CSE's current operation mode is normal, otherwise false.
 189  */
 190 bool cse_is_hfs1_com_normal(void);
 191
 192 /*
 193  * Checks CSE's current operation mode is SECOVER_MEI_MSG or not.
 194  * Returns true if CSE's current operation mode is SECOVER_MEI_MSG, otherwise false.
 195  */
 196 bool cse_is_hfs1_com_secover_mei_msg(void);
 197
 198 /*
 199  * Checks CSE's current operation mode is Soft Disable Mode or not.
 200  * Returns true if CSE's current operation mode is Soft Disable Mode, otherwise false.
 201  */
 202 bool cse_is_hfs1_com_soft_temp_disable(void);
 203
 204 /*
 205  * Checks CSE's Firmware SKU is Custom or not.
 206  * Returns true if CSE's Firmware SKU is Custom, otherwise false
 207  */
 208 bool cse_is_hfs3_fw_sku_custom(void);
 209
 210 /*
 211  * Polls for CSE's current operation mode 'Soft Temp Disable'.
 212  * Returns 0 on failure and 1 on success.
 213  */
 214 uint8_t cse_wait_com_soft_temp_disable(void);
 215
 216 /*
 217  * The CSE Custom SKU supports notion of RO and RW boot partitions. The function will set
 218  * CSE's boot partition as per Chrome OS boot modes. In normal mode, the function allows CSE to
 219  * boot from RW and triggers recovery mode if CSE fails to jump to RW.
 220  * In software triggered recovery mode, the function allows CSE to boot from whatever is
 221  * currently selected partition.
 222  */
 223 void cse_fw_sync(void *unused);
 224 #endif // SOC_INTEL_COMMON_CSE_H