src/soc/intel/apollolake/lpc.c

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #include <device/pci.h>
   5 #include <intelblocks/lpc_lib.h>
   6 #include <intelblocks/rtc.h>
   7 #include <soc/gpio.h>
   8 #include <soc/pcr_ids.h>
   9 #include <soc/pm.h>
  10 #include "chip.h"
  11
  12 static const struct lpc_mmio_range apl_lpc_fixed_mmio_ranges[] = {
  13         { 0xfed40000, 0x8000 },
  14         { 0xfedc0000, 0x4000 },
  15         { 0xfed20800, 16 },
  16         { 0xfed20880, 8 },
  17         { 0xfed208e0, 16 },
  18         { 0xfed208f0, 8 },
  19         { 0xfed30800, 16 },
  20         { 0xfed30880, 8 },
  21         { 0xfed308e0, 16 },
  22         { 0xfed308f0, 8 },
  23         { 0, 0 }
  24 };
  25
  26 const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
  27 {
  28         return apl_lpc_fixed_mmio_ranges;
  29 }
  30
  31 static const struct pad_config lpc_gpios[] = {
  32 #if CONFIG(SOC_INTEL_GLK)
  33 #if !CONFIG(SOC_ESPI)
  34         PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */
  35         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, NONE, DEEP, NF1, HIZCRx1,
  36                 DISPUPD), /* LPC_CLKOUT0 */
  37         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_149, NONE, DEEP, NF1, HIZCRx1,
  38                 DISPUPD), /* LPC_CLKOUT1 */
  39         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_150, UP_20K, DEEP, NF1, HIZCRx1,
  40                 DISPUPD), /* LPC_AD0 */
  41         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF1, HIZCRx1,
  42                 DISPUPD), /* LPC_AD1 */
  43         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_152, UP_20K, DEEP, NF1, HIZCRx1,
  44                 DISPUPD), /* LPC_AD2 */
  45         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_153, UP_20K, DEEP, NF1, HIZCRx1,
  46                 DISPUPD), /* LPC_AD3 */
  47         PAD_CFG_NF(GPIO_154, UP_20K, DEEP, NF1), /* LPC_CLKRUNB */
  48         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1,
  49                 DISPUPD), /* LPC_FRAMEB */
  50 #else
  51         /*
  52          * LPC_CLKRUNB should be in GPIO mode for eSPI. Other pin settings
  53          * i.e. Rx path enable/disable, Tx path enable/disable, pull up
  54          * enable/disable etc are ignored. Leaving this pin in Native mode
  55          * will keep LPC Controller awake and prevent S0ix entry
  56          */
  57         PAD_NC(GPIO_154, NONE),
  58 #endif /* !CONFIG(SOC_ESPI) */
  59 #else
  60         PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
  61         PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),
  62         PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),
  63         PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),
  64         PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),
  65         PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),
  66         PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),
  67         PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1),
  68         PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
  69 #endif
  70 };
  71
  72 void lpc_configure_pads(void)
  73 {
  74         gpio_configure_pads(lpc_gpios, ARRAY_SIZE(lpc_gpios));
  75 }
  76
  77 void lpc_soc_init(struct device *dev)
  78 {
  79         const struct soc_intel_apollolake_config *cfg;
  80         cfg = config_of(dev);
  81
  82         /* Set LPC Serial IRQ mode */
  83         lpc_set_serirq_mode(cfg->serirq_mode);
  84
  85         /* Initialize RTC */
  86         rtc_init();
  87 }