src/soc/intel/apollolake/include/soc/pci_devs.h

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #ifndef _SOC_APOLLOLAKE_PCI_DEVS_H_
   5 #define _SOC_APOLLOLAKE_PCI_DEVS_H_
   6
   7 #include <device/pci_def.h>
   8
   9 #define _PCH_DEVFN(slot, func)  PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
  10
  11 #if !defined(__SIMPLE_DEVICE__)
  12 #include <device/device.h>
  13 #define _PCH_DEV(slot, func)    pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
  14 #else
  15 #define _PCH_DEV(slot, func)    PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
  16 #endif
  17
  18 /* System Agent Devices */
  19
  20 #define SA_DEV_SLOT_ROOT        0x00
  21 #define  SA_DEVFN_ROOT          PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)
  22 #if defined(__SIMPLE_DEVICE__)
  23 #define  SA_DEV_ROOT            PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
  24 #endif
  25
  26 #define SA_DEV_SLOT_PUNIT       0x01
  27 #define  SA_DEVFN_PUNIT         PCI_DEVFN(SA_DEV_SLOT_PUNIT, 0)
  28 #define  SA_DEV_PUNIT           PCI_DEV(0, SA_DEV_SLOT_PUNIT, 0)
  29
  30 #define SA_DEV_SLOT_IGD         0x02
  31 #define  SA_DEVFN_IGD           PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
  32 #define  SA_DEV_IGD             PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
  33
  34 #define SA_DEV_SLOT_IPU         0x03
  35 #define  SA_DEVFN_IPU           PCI_DEVFN(SA_DEV_SLOT_IPU, 0)
  36 #define  SA_DEV_IPU             PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
  37
  38 #define SA_GLK_DEV_SLOT_GMM             0x03
  39 #define SA_GLK_DEVFN_GMM                PCI_DEVFN(SA_GLK_DEV_SLOT_GMM, 0)
  40 #define SA_GLK_DEV_GMM          PCI_DEV(0, SA_GLK_DEV_SLOT_GMM, 0)
  41
  42 /* PCH Devices */
  43
  44 #define PCH_DEV_SLOT_NPK        0x00
  45 #define  PCH_DEVFN_NPK          _PCH_DEVFN(NPK, 2)
  46 #define  PCH_DEV_NPK            _PCH_DEV(NPK,2)
  47
  48 #define PCH_DEV_SLOT_CNVI       0x0c
  49 #define  PCH_DEVFN_CNVI         _PCH_DEVFN(CNVI, 0)
  50 #define  PCH_DEV_CNVI           _PCH_DEV(CNVI, 0)
  51
  52 #define PCH_DEV_SLOT_P2SB       0x0d
  53 #define  PCH_DEVFN_P2SB         _PCH_DEVFN(P2SB, 0)
  54 #define  PCH_DEVFN_PMC          _PCH_DEVFN(P2SB, 1)
  55 #define  PCH_DEVFN_SPI          _PCH_DEVFN(P2SB, 2)
  56 #define  PCH_DEV_P2SB           _PCH_DEV(P2SB, 0)
  57 #define  PCH_DEV_PMC            _PCH_DEV(P2SB, 1)
  58 #define  PCH_DEV_SPI            _PCH_DEV(P2SB, 2)
  59
  60 #define PCH_DEV_SLOT_HDA        0x0e
  61 #define  PCH_DEVFN_HDA          _PCH_DEVFN(HDA, 0)
  62 #define  PCH_DEV_HDA            _PCH_DEV(HDA, 0)
  63
  64 #define PCH_DEV_SLOT_CSE        0x0f
  65 #define  PCH_DEVFN_CSE          _PCH_DEVFN(CSE, 0)
  66 #define  PCH_DEV_CSE            _PCH_DEV(CSE, 0)
  67
  68 #define PCH_DEV_SLOT_ISH        0x11
  69 #define  PCH_DEVFN_ISH          _PCH_DEVFN(ISH, 0)
  70 #define  PCH_DEV_ISH            _PCH_DEV(ISH, 0)
  71
  72 #define PCH_DEV_SLOT_SATA       0x12
  73 #define  PCH_DEVFN_SATA         _PCH_DEVFN(SATA, 0)
  74 #define  PCH_DEV_SATA           _PCH_DEV(SATA, 0)
  75
  76 #define PCH_DEV_SLOT_PCIE       0x13
  77 #define  PCH_DEVFN_PCIE1        _PCH_DEVFN(PCIE, 0)
  78 #define  PCH_DEVFN_PCIE2        _PCH_DEVFN(PCIE, 1)
  79 #define  PCH_DEVFN_PCIE3        _PCH_DEVFN(PCIE, 2)
  80 #define  PCH_DEVFN_PCIE4        _PCH_DEVFN(PCIE, 3)
  81 #define  PCH_DEV_PCIE1          _PCH_DEV(PCIE, 0)
  82 #define  PCH_DEV_PCIE2          _PCH_DEV(PCIE, 1)
  83 #define  PCH_DEV_PCIE3          _PCH_DEV(PCIE, 2)
  84 #define  PCH_DEV_PCIE4          _PCH_DEV(PCIE, 3)
  85
  86 #define PCH_DEV_SLOT_PCIE_1     0x14
  87 #define  PCH_DEVFN_PCIE5        _PCH_DEVFN(PCIE_1, 0)
  88 #define  PCH_DEVFN_PCIE6        _PCH_DEVFN(PCIE_1, 1)
  89 #define  PCH_DEV_PCIE5          _PCH_DEV(PCIE_1, 0)
  90 #define  PCH_DEV_PCIE6          _PCH_DEV(PCIE_1, 1)
  91
  92 #define PCH_DEV_SLOT_XHCI       0x15
  93 #define  PCH_DEVFN_XHCI         _PCH_DEVFN(XHCI, 0)
  94 #define  PCH_DEVFN_XDCI         _PCH_DEVFN(XHCI, 1)
  95 #define  PCH_DEV_XHCI           _PCH_DEV(XHCI, 0)
  96 #define  PCH_DEV_XDCI           _PCH_DEV(XHCI, 1)
  97
  98 /* LPSS I2C, 2 devices cover 8 controllers */
  99 #define PCH_DEV_SLOT_SIO1       0x16
 100 #define  PCH_DEVFN_I2C0         _PCH_DEVFN(SIO1, 0)
 101 #define  PCH_DEVFN_I2C1         _PCH_DEVFN(SIO1, 1)
 102 #define  PCH_DEVFN_I2C2         _PCH_DEVFN(SIO1, 2)
 103 #define  PCH_DEVFN_I2C3         _PCH_DEVFN(SIO1, 3)
 104 #define  PCH_DEV_I2C0           _PCH_DEV(SIO1, 0)
 105 #define  PCH_DEV_I2C1           _PCH_DEV(SIO1, 1)
 106 #define  PCH_DEV_I2C2           _PCH_DEV(SIO1, 2)
 107 #define  PCH_DEV_I2C3           _PCH_DEV(SIO1, 3)
 108
 109 #define PCH_DEV_SLOT_SIO2       0x17
 110 #define  PCH_DEVFN_I2C4         _PCH_DEVFN(SIO2, 0)
 111 #define  PCH_DEVFN_I2C5         _PCH_DEVFN(SIO2, 1)
 112 #define  PCH_DEVFN_I2C6         _PCH_DEVFN(SIO2, 2)
 113 #define  PCH_DEVFN_I2C7         _PCH_DEVFN(SIO2, 3)
 114 #define  PCH_DEV_I2C4           _PCH_DEV(SIO2, 0)
 115 #define  PCH_DEV_I2C5           _PCH_DEV(SIO2, 1)
 116 #define  PCH_DEV_I2C6           _PCH_DEV(SIO2, 2)
 117 #define  PCH_DEV_I2C7           _PCH_DEV(SIO2, 3)
 118
 119 /* LPSS UART */
 120 #define PCH_DEV_SLOT_UART       0x18
 121 #define  PCH_DEVFN_UART0        _PCH_DEVFN(UART, 0)
 122 #define  PCH_DEVFN_UART1        _PCH_DEVFN(UART, 1)
 123 #define  PCH_DEVFN_UART2        _PCH_DEVFN(UART, 2)
 124 #define  PCH_DEVFN_UART3        _PCH_DEVFN(UART, 3)
 125 #define  PCH_DEV_UART0          _PCH_DEV(UART, 0)
 126 #define  PCH_DEV_UART1          _PCH_DEV(UART, 1)
 127 #define  PCH_DEV_UART2          _PCH_DEV(UART, 2)
 128 #define  PCH_DEV_UART3          _PCH_DEV(UART, 3)
 129
 130 /* LPSS SPI */
 131 #define PCH_DEV_SLOT_SPI        0x19
 132 #define  PCH_DEVFN_SPI0         _PCH_DEVFN(SPI, 0)
 133 #define  PCH_DEVFN_SPI1         _PCH_DEVFN(SPI, 1)
 134 #define  PCH_DEVFN_SPI2         _PCH_DEVFN(SPI, 2)
 135 #define  PCH_DEV_SPI0           _PCH_DEV(SPI, 0)
 136 #define  PCH_DEV_SPI1           _PCH_DEV(SPI, 1)
 137 #define  PCH_DEV_SPI2           _PCH_DEV(SPI, 2)
 138
 139 /* LPSS PWM */
 140 #define PCH_DEV_SLOT_PWM        0x1a
 141 #define  PCH_DEVFN_PWM          _PCH_DEVFN(PWM, 0)
 142 #define  PCH_DEV_PWM            _PCH_DEV(PWM, 0)
 143
 144 #define PCH_DEV_SLOT_SDCARD     0x1b
 145 #define  PCH_DEVFN_SDCARD       _PCH_DEVFN(SDCARD, 0)
 146 #define  PCH_DEV_SDCARD         _PCH_DEV(SDCARD, 0)
 147
 148 #define PCH_DEV_SLOT_EMMC       0x1c
 149 #define  PCH_DEVFN_EMMC         _PCH_DEVFN(EMMC, 0)
 150 #define  PCH_DEV_EMMC           _PCH_DEV(EMMC, 0)
 151
 152 #define PCH_DEV_SLOT_SDIO       0x1e
 153 #define  PCH_DEVFN_SDIO         _PCH_DEVFN(SDIO, 0)
 154 #define  PCH_DEV_SDIO           _PCH_DEV(SDIO, 0)
 155
 156 #define PCH_DEV_SLOT_LPC        0x1f
 157 #define  PCH_DEVFN_LPC          _PCH_DEVFN(LPC, 0)
 158 #define  PCH_DEVFN_SMBUS        _PCH_DEVFN(LPC, 1)
 159 #define  PCH_DEV_LPC            _PCH_DEV(LPC, 0)
 160 #define  PCH_DEV_SMBUS          _PCH_DEV(LPC, 1)
 161
 162 #endif