src/soc/intel/apollolake/include/soc/iomap.h

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #ifndef _SOC_APOLLOLAKE_IOMAP_H_
   5 #define _SOC_APOLLOLAKE_IOMAP_H_
   6
   7 #include <commonlib/helpers.h>
   8
   9 #define P2SB_BAR                        CONFIG_PCR_BASE_ADDRESS
  10 #define P2SB_SIZE                       (16 * MiB)
  11 #define MCH_BASE_ADDRESS                0xfed10000
  12 #define MCH_BASE_SIZE                   (32 * KiB)
  13
  14 #define HPET_BASE_ADDRESS               0xfed00000
  15
  16 #define ACPI_BASE_ADDRESS               0x400
  17 #define ACPI_BASE_SIZE                  0x100
  18 #define R_ACPI_PM1_TMR                  0x8
  19
  20 #define TCO_BASE_ADDRESS        (ACPI_BASE_ADDRESS + 0x60)
  21 #define TCO_BASE_SIZE           0x20
  22
  23 /* CST Range (R/W) IO port block size */
  24 #define PMG_IO_BASE_CST_RNG_BLK_SIZE    0x5
  25 /* ACPI PMIO Offset to C-state register*/
  26 #define ACPI_PMIO_CST_REG       (ACPI_BASE_ADDRESS + 0x14)
  27
  28 /* Accesses to these BARs are hardcoded in FSP */
  29 #define PMC_BAR0                        0xfe042000
  30 #define PMC_BAR1                        0xfe044000
  31 #define PMC_BAR0_SIZE                   (8 * KiB)
  32
  33 #define SRAM_BASE_0                     0xfe900000
  34 #define SRAM_SIZE_0                     (8 * KiB)
  35 #define SRAM_BASE_2                     0xfe902000
  36 #define SRAM_SIZE_2                     (4 * KiB)
  37
  38 #define HECI1_BASE_ADDRESS              0xfed1a000
  39 #define PSF3_BASE_ADDRESS               0x1e00
  40
  41 /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */
  42 #define SPI_BASE_ADDRESS                0xfe010000
  43 #define EARLY_GSPI_BASE_ADDRESS         0xfe011000
  44
  45 /* Temporary BAR for early I2C bus access */
  46 #define EARLY_I2C_BASE_ADDRESS          0xfe020000
  47 #define EARLY_I2C_BASE(x)       (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
  48
  49 #define ABOVE_4GB_MEM_BASE_ADDRESS      (128ULL * GiB)
  50 #define ABOVE_4GB_MEM_BASE_SIZE (64ULL * GiB)
  51
  52 #endif /* _SOC_APOLLOLAKE_IOMAP_H_ */