src/soc/intel/apollolake/include/soc/cpu.h

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #ifndef _SOC_APOLLOLAKE_CPU_H_
   5 #define _SOC_APOLLOLAKE_CPU_H_
   6
   7 #include <cpu/x86/msr.h>
   8 #include <intelblocks/msr.h>
   9
  10 /* Common Timer Copy (CTC) frequency - 19.2MHz. */
  11 #define CTC_FREQ                19200000
  12
  13 struct device;
  14 void apollolake_init_cpus(struct device *dev);
  15 void mainboard_devtree_update(struct device *dev);
  16
  17 /* Flush L1D to L2 */
  18 static inline void flush_l1d_to_l2(void)
  19 {
  20         msr_t msr = rdmsr(MSR_POWER_MISC);
  21         msr.lo |= FLUSH_DL1_L2;
  22         wrmsr(MSR_POWER_MISC, msr);
  23 }
  24 #endif /* _SOC_APOLLOLAKE_CPU_H_ */