src/soc/intel/apollolake/cpu.c

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #include <acpi/acpi.h>
   5 #include <assert.h>
   6 #include <console/console.h>
   7 #include "chip.h"
   8 #include <cpu/cpu.h>
   9 #include <cpu/x86/lapic.h>
  10 #include <cpu/x86/mp.h>
  11 #include <cpu/intel/microcode.h>
  12 #include <cpu/intel/turbo.h>
  13 #include <cpu/x86/msr.h>
  14 #include <cpu/x86/mtrr.h>
  15 #include <cpu/x86/smm.h>
  16 #include <cpu/intel/em64t100_save_state.h>
  17 #include <cpu/intel/smm_reloc.h>
  18 #include <device/device.h>
  19 #include <device/pci.h>
  20 #include <fsp/api.h>
  21 #include <intelblocks/cpulib.h>
  22 #include <intelblocks/fast_spi.h>
  23 #include <intelblocks/mp_init.h>
  24 #include <intelblocks/msr.h>
  25 #include <intelblocks/sgx.h>
  26 #include <reg_script.h>
  27 #include <romstage_handoff.h>
  28 #include <soc/cpu.h>
  29 #include <soc/iomap.h>
  30 #include <soc/pci_devs.h>
  31 #include <soc/pm.h>
  32
  33 static const struct reg_script core_msr_script[] = {
  34 #if !CONFIG(SOC_INTEL_GLK)
  35         /* Enable C-state and IO/MWAIT redirect */
  36         REG_MSR_WRITE(MSR_PKG_CST_CONFIG_CONTROL,
  37                 (PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK
  38                 | IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK)),
  39         /* Power Management I/O base address for I/O trapping to C-states */
  40         REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE,
  41                 (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))),
  42         /* Disable support for MONITOR and MWAIT instructions */
  43         REG_MSR_RMW(IA32_MISC_ENABLE, ~MONITOR_MWAIT_DIS_MASK, 0),
  44 #endif
  45         /* Disable C1E */
  46         REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0),
  47         /*
  48          * Enable and Lock the Advanced Encryption Standard (AES-NI)
  49          * feature register
  50          */
  51         REG_MSR_RMW(MSR_FEATURE_CONFIG, ~FEATURE_CONFIG_RESERVED_MASK,
  52                 FEATURE_CONFIG_LOCK),
  53         REG_SCRIPT_END
  54 };
  55
  56 void soc_core_init(struct device *cpu)
  57 {
  58         /* Clear out pending MCEs */
  59         /* TODO(adurbin): Some of these banks are core vs package
  60                           scope. For now every CPU clears every bank. */
  61         if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE) || acpi_get_sleep_type() == ACPI_S5)
  62                 mca_configure();
  63
  64         /* Set core MSRs */
  65         reg_script_run(core_msr_script);
  66         /*
  67          * Enable ACPI PM timer emulation, which also lets microcode know
  68          * location of ACPI_BASE_ADDRESS. This also enables other features
  69          * implemented in microcode.
  70         */
  71         enable_pm_timer_emulation();
  72
  73         /* Configure Core PRMRR for SGX. */
  74         if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
  75                 prmrr_core_configure();
  76
  77         /* Set Max Non-Turbo ratio if RAPL is disabled. */
  78         if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
  79                 cpu_set_p_state_to_max_non_turbo_ratio();
  80                 /* Disable speed step */
  81                 cpu_set_eist(false);
  82         } else if (CONFIG(APL_SET_MIN_CLOCK_RATIO)) {
  83                 cpu_set_p_state_to_min_clock_ratio();
  84                 /* Disable speed step */
  85                 cpu_set_eist(false);
  86         }
  87 }
  88
  89 #if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
  90 static void soc_init_core(struct device *cpu)
  91 {
  92         soc_core_init(cpu);
  93 }
  94
  95 static struct device_operations cpu_dev_ops = {
  96         .init = soc_init_core,
  97 };
  98
  99 static const struct cpu_device_id cpu_table[] = {
 100         { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 },
 101         { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 },
 102         { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 },
 103         { X86_VENDOR_INTEL, CPUID_GLK_A0 },
 104         { X86_VENDOR_INTEL, CPUID_GLK_B0 },
 105         { X86_VENDOR_INTEL, CPUID_GLK_R0 },
 106         { 0, 0 },
 107 };
 108
 109 static const struct cpu_driver driver __cpu_driver = {
 110         .ops      = &cpu_dev_ops,
 111         .id_table = cpu_table,
 112 };
 113 #endif
 114
 115 /*
 116  * MP and SMM loading initialization.
 117  */
 118 struct smm_relocation_attrs {
 119         uint32_t smbase;
 120         uint32_t smrr_base;
 121         uint32_t smrr_mask;
 122 };
 123
 124 static struct smm_relocation_attrs relo_attrs;
 125
 126 /*
 127  * Do essential initialization tasks before APs can be fired up.
 128  *
 129  * IF (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) -
 130  * Skip Pre MP init MTRR programming, as MTRRs are mirrored from BSP,
 131  * that are set prior to ramstage.
 132  * Real MTRRs are programmed after resource allocation.
 133  *
 134  * Do FSP loading before MP Init to ensure that the FSP component stored in
 135  * external stage cache in TSEG does not flush off due to SMM relocation
 136  * during MP Init stage.
 137  *
 138  * ELSE -
 139  * Enable MTRRs on the BSP. This creates the MTRR solution that the
 140  * APs will use. Otherwise APs will try to apply the incomplete solution
 141  * as the BSP is calculating it.
 142  */
 143 static void pre_mp_init(void)
 144 {
 145         if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) {
 146                 fsps_load(romstage_handoff_is_resume());
 147                 return;
 148         }
 149         x86_setup_mtrrs_with_detect();
 150         x86_mtrr_check();
 151
 152         /* Enable the local CPU apics */
 153         setup_lapic();
 154 }
 155
 156 #if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
 157 static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt)
 158 {
 159         msr_t msr;
 160         msr = rdmsr(MSR_CORE_THREAD_COUNT);
 161         *num_virt = (msr.lo >> 0) & 0xffff;
 162         *num_phys = (msr.lo >> 16) & 0xffff;
 163 }
 164
 165 /* Find CPU topology */
 166 int get_cpu_count(void)
 167 {
 168         unsigned int num_virt_cores, num_phys_cores;
 169
 170         read_cpu_topology(&num_phys_cores, &num_virt_cores);
 171
 172         printk(BIOS_DEBUG, "Detected %u core, %u thread CPU.\n",
 173                num_phys_cores, num_virt_cores);
 174
 175         return num_virt_cores;
 176 }
 177
 178 void get_microcode_info(const void **microcode, int *parallel)
 179 {
 180         *microcode = intel_microcode_find();
 181         *parallel = 1;
 182
 183         /* Make sure BSP is using the microcode from cbfs */
 184         intel_microcode_load_unlocked(*microcode);
 185 }
 186 #endif
 187
 188 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 189                                 size_t *smm_save_state_size)
 190 {
 191         uintptr_t smm_base;
 192         size_t smm_size;
 193         uintptr_t handler_base;
 194         size_t handler_size;
 195
 196         /* All range registers are aligned to 4KiB */
 197         const uint32_t rmask = ~((1 << 12) - 1);
 198
 199         /* Initialize global tracking state. */
 200         smm_region(&smm_base, &smm_size);
 201         smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
 202
 203         relo_attrs.smbase = smm_base;
 204         relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
 205         relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
 206         relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
 207
 208         *perm_smbase = handler_base;
 209         *perm_smsize = handler_size;
 210         *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
 211 }
 212
 213 static void relocation_handler(int cpu, uintptr_t curr_smbase,
 214                                 uintptr_t staggered_smbase)
 215 {
 216         msr_t smrr;
 217         em64t100_smm_state_save_area_t *smm_state;
 218         /* Set up SMRR. */
 219         smrr.lo = relo_attrs.smrr_base;
 220         smrr.hi = 0;
 221         wrmsr(IA32_SMRR_PHYS_BASE, smrr);
 222         smrr.lo = relo_attrs.smrr_mask;
 223         smrr.hi = 0;
 224         wrmsr(IA32_SMRR_PHYS_MASK, smrr);
 225         smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
 226         smm_state->smbase = staggered_smbase;
 227 }
 228 /*
 229  * CPU initialization recipe
 230  *
 231  * Note that no microcode update is passed to the init function. CSE updates
 232  * the microcode on all cores before releasing them from reset. That means that
 233  * the BSP and all APs will come up with the same microcode revision.
 234  */
 235
 236 static void post_mp_init(void)
 237 {
 238         smm_southbridge_enable(PWRBTN_EN | GBL_EN);
 239
 240         if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
 241                 mp_run_on_all_cpus(sgx_configure, NULL);
 242 }
 243
 244 static const struct mp_ops mp_ops = {
 245         .pre_mp_init = pre_mp_init,
 246         .get_cpu_count = get_cpu_count,
 247         .get_smm_info = get_smm_info,
 248         .get_microcode_info = get_microcode_info,
 249         .pre_mp_smm_init = smm_southbridge_clear_state,
 250         .relocation_handler = relocation_handler,
 251         .post_mp_init = post_mp_init,
 252 };
 253
 254 void soc_init_cpus(struct bus *cpu_bus)
 255 {
 256         /* Clear for take-off */
 257         if (mp_init_with_smm(cpu_bus, &mp_ops))
 258                 printk(BIOS_ERR, "MP initialization failure.\n");
 259 }
 260
 261 void apollolake_init_cpus(struct device *dev)
 262 {
 263         if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT))
 264                 return;
 265         soc_init_cpus(dev->link_list);
 266
 267         /* Temporarily cache the memory-mapped boot media. */
 268         if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) &&
 269                 CONFIG(BOOT_DEVICE_SPI_FLASH))
 270                 fast_spi_cache_bios_region();
 271 }