src/soc/intel/apollolake/acpi/pci_irqs.asl

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #include "soc_int.asl"
   5
   6 Method(_PRT)
   7 {
   8         Return(Package() {
   9
  10                 Package(){0x0000FFFF, 0, 0, NPK_INT},
  11                 Package(){0x0000FFFF, 1, 0, PUNIT_INT},
  12                 Package(){0x0002FFFF, 0, 0, GEN_INT},
  13                 Package(){0x0003FFFF, 0, 0, IUNIT_INT},
  14                 Package(){0x000DFFFF, 1, 0, PMC_INT},
  15                 Package(){0x000EFFFF, 0, 0, AUDIO_INT},
  16                 Package(){0x000FFFFF, 0, 0, CSE_INT},
  17                 Package(){0x0011FFFF, 0, 0, ISH_INT},
  18                 Package(){0x0012FFFF, 0, 0, SATA_INT},
  19 #if CONFIG(SOC_INTEL_GLK)
  20                 Package(){0x000CFFFF, 0, 0, CNVI_INT},
  21                 Package(){0x0013FFFF, 0, 0, PIRQF_INT},
  22                 Package(){0x0013FFFF, 1, 0, PIRQF_INT},
  23                 Package(){0x0013FFFF, 2, 0, PIRQF_INT},
  24                 Package(){0x0013FFFF, 3, 0, PIRQF_INT},
  25                 Package(){0x0014FFFF, 0, 0, PIRQG_INT},
  26                 Package(){0x0014FFFF, 1, 0, PIRQG_INT},
  27 #else
  28                 Package(){0x0013FFFF, 0, 0, PIRQA_INT},
  29                 Package(){0x0013FFFF, 1, 0, PIRQB_INT},
  30                 Package(){0x0013FFFF, 2, 0, PIRQC_INT},
  31                 Package(){0x0013FFFF, 3, 0, PIRQD_INT},
  32                 Package(){0x0014FFFF, 0, 0, PIRQB_INT},
  33                 Package(){0x0014FFFF, 1, 0, PIRQC_INT},
  34                 Package(){0x0014FFFF, 2, 0, PIRQD_INT},
  35                 Package(){0x0014FFFF, 3, 0, PIRQA_INT},
  36 #endif
  37                 Package(){0x0015FFFF, 0, 0, XHCI_INT},
  38                 Package(){0x0015FFFF, 1, 0, XDCI_INT},
  39                 Package(){0x0016FFFF, 0, 0, I2C0_INT},
  40                 Package(){0x0016FFFF, 1, 0, I2C1_INT},
  41                 Package(){0x0016FFFF, 2, 0, I2C2_INT},
  42                 Package(){0x0016FFFF, 3, 0, I2C3_INT},
  43                 Package(){0x0017FFFF, 0, 0, I2C4_INT},
  44                 Package(){0x0017FFFF, 1, 0, I2C5_INT},
  45                 Package(){0x0017FFFF, 2, 0, I2C6_INT},
  46                 Package(){0x0017FFFF, 3, 0, I2C7_INT},
  47                 Package(){0x0018FFFF, 0, 0, UART0_INT},
  48                 Package(){0x0018FFFF, 1, 0, UART1_INT},
  49                 Package(){0x0018FFFF, 2, 0, UART2_INT},
  50                 Package(){0x0018FFFF, 3, 0, UART3_INT},
  51                 Package(){0x0019FFFF, 0, 0, SPI0_INT},
  52                 Package(){0x0019FFFF, 1, 0, SPI1_INT},
  53                 Package(){0x0019FFFF, 2, 0, SPI2_INT},
  54                 Package(){0x001BFFFF, 0, 0, SDCARD_INT},
  55                 Package(){0x001CFFFF, 0, 0, EMMC_INT},
  56                 Package(){0x001EFFFF, 0, 0, SDIO_INT},
  57                 Package(){0x001FFFFF, 1, 0, SMBUS_INT},
  58         })
  59 }