src/northbridge/intel/x4x/romstage.c

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #include <device/pci_ops.h>
   5 #include <console/console.h>
   6 #include <southbridge/intel/common/pmclib.h>
   7 #include <northbridge/intel/x4x/x4x.h>
   8 #include <arch/romstage.h>
   9
  10 #if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
  11 #include <southbridge/intel/i82801jx/i82801jx.h>
  12 #elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
  13 #include <southbridge/intel/i82801gx/i82801gx.h>
  14 #endif
  15
  16 __weak void mb_pre_raminit_setup(int s3_resume)
  17 {
  18 }
  19
  20 void mainboard_romstage_entry(void)
  21 {
  22         u8 spd_addr_map[4] = {};
  23         u8 boot_path = 0;
  24         u8 s3_resume;
  25
  26 #if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
  27         i82801jx_early_init();
  28 #elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
  29         i82801gx_early_init();
  30 #endif
  31
  32         x4x_early_init();
  33
  34         s3_resume = southbridge_detect_s3_resume();
  35         mb_pre_raminit_setup(s3_resume);
  36
  37         if (s3_resume)
  38                 boot_path = BOOT_PATH_RESUME;
  39         if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
  40                 boot_path = BOOT_PATH_WARM_RESET;
  41
  42         mb_get_spd_map(spd_addr_map);
  43         sdram_initialize(boot_path, spd_addr_map);
  44
  45         x4x_late_init(s3_resume);
  46
  47         printk(BIOS_DEBUG, "x4x late init complete\n");
  48 }