1 /* This file is part of the coreboot project. */
2 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 #ifndef _SKXSP_TP_IIO_H_
5 #define _SKXSP_TP_IIO_H_
8 #include <soc/pci_devs.h>
10 enum tp_iio_bifur_table_index
{
24 * Standard Tioga Pass Iio Bifurcation Table
25 * This is SS 2x16 config. As documented in OCP TP spec, there are
26 * 3 configs. SS 2x16 is the most common.
27 * TODO: figure out config through board SKU ID and through PCIe
28 * config GPIO setting (SLT_CFG0 / SLT_CFG1).
30 static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table
[] = {
31 { Iio_Socket0
, Iio_Iou0
, IIO_BIFURCATE_xxxxxx16
}, /* 1A x16 */
32 { Iio_Socket0
, Iio_Iou1
, IIO_BIFURCATE_xxxxxx16
}, /* 2A x16 */
33 { Iio_Socket0
, Iio_Iou2
, IIO_BIFURCATE_xxxxxx16
}, /* 3A x16 */
34 { Iio_Socket0
, Iio_Mcp0
, IIO_BIFURCATE_xxxxxxxx
}, /* No MCP */
35 { Iio_Socket0
, Iio_Mcp1
, IIO_BIFURCATE_xxxxxxxx
}, /* No MCP */
36 { Iio_Socket1
, Iio_Iou0
, IIO_BIFURCATE_xxxxxxxx
}, /* no IOU0 */
37 { Iio_Socket1
, Iio_Iou1
, IIO_BIFURCATE_xxxxxxxx
}, /* no IOU1 */
38 { Iio_Socket1
, Iio_Iou2
, IIO_BIFURCATE_xxx8xxx8
}, /* 3A x8, 3C x8 */
39 { Iio_Socket1
, Iio_Mcp0
, IIO_BIFURCATE_xxxxxxxx
}, /* No MCP */
40 { Iio_Socket1
, Iio_Mcp1
, IIO_BIFURCATE_xxxxxxxx
}, /* No MCP */
44 * Standard Tioga Pass Iio PCIe Port Table
46 static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0
[] = {
47 // PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload |
48 // DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd |
49 // NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 |
50 // NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 |
51 // NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride
52 { PORT_1A
, NOT_HIDE
, 0x00, PcieAuto
, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
53 NTB_PORT_TRANSPARENT
, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
55 { PORT_1B
, HIDE
, 0x00, PcieAuto
, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
56 NTB_PORT_TRANSPARENT
, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
58 { PORT_1C
, HIDE
, 0x00, PcieAuto
, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
59 NTB_PORT_TRANSPARENT
, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
61 { PORT_1D
, HIDE
, 0x00, PcieAuto
, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
62 NTB_PORT_TRANSPARENT
, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
64 { PORT_2A
, NOT_HIDE
, 0x00, PcieAuto
, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
65 NTB_PORT_TRANSPARENT
, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
67 { PORT_2B
, HIDE
, 0x00, PcieAuto
, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
68 NTB_PORT_TRANSPARENT
, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
70 { PORT_2C
, HIDE
, 0x00, PcieAuto
, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
71 NTB_PORT_TRANSPARENT
, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
73 { PORT_2D
, HIDE
, 0x00, PcieAuto
, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
74 NTB_PORT_TRANSPARENT
, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
76 { PORT_3A
, NOT_HIDE
, 0x00, PcieAuto
, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
77 NTB_PORT_TRANSPARENT
, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
79 { PORT_3B
, HIDE
, 0x00, PcieAuto
, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
80 NTB_PORT_TRANSPARENT
, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
82 { PORT_3C
, NOT_HIDE
, 0x00, PcieAuto
, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
83 NTB_PORT_TRANSPARENT
, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
85 { PORT_3D
, HIDE
, 0x00, PcieAuto
, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
86 NTB_PORT_TRANSPARENT
, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
91 * Standard Tioga Pass PCH PCIe Port Table
93 static const UPD_PCH_PCIE_PORT tp_pch_pci_port_skt0
[] = {
94 //PortIndex ; ForceEnable ; PortLinkSpeed
95 { 0x00, 0x00, PcieAuto
},
96 { 0x04, 0x00, PcieAuto
},
97 { 0x05, 0x00, PcieAuto
},
100 #endif /* _SKXSP_TP_IIO_H_ */