src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #ifndef _SKXSP_TP_IIO_H_
   5 #define _SKXSP_TP_IIO_H_
   6
   7 #include <FspmUpd.h>
   8 #include <soc/pci_devs.h>
   9
  10 enum tp_iio_bifur_table_index {
  11         Skt0_Iou0 = 0,
  12         Skt0_Iou1,
  13         Skt0_Iou2,
  14         Skt0_Mcp0,
  15         Skt0_Mcp1,
  16         Skt1_Iou0,
  17         Skt1_Iou1,
  18         Skt1_Iou2,
  19         Skt1_Mcp0,
  20         Skt1_Mcp1
  21 };
  22
  23 /*
  24  * Standard Tioga Pass Iio Bifurcation Table
  25  * This is SS 2x16 config. As documented in OCP TP spec, there are
  26  * 3 configs. SS 2x16 is the most common.
  27  * TODO: figure out config through board SKU ID and through PCIe
  28  * config GPIO setting (SLT_CFG0 / SLT_CFG1).
  29  */
  30 static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[] = {
  31         { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, /* 1A x16 */
  32         { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, /* 2A x16 */
  33         { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, /* 3A x16 */
  34         { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
  35         { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
  36         { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxxxx }, /* no IOU0 */
  37         { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxxxx }, /* no IOU1 */
  38         { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 }, /* 3A x8, 3C x8 */
  39         { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
  40         { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
  41 };
  42
  43 /*
  44  * Standard Tioga Pass Iio PCIe Port Table
  45  */
  46 static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[] = {
  47         // PortIndex |  HidePort  | DeEmphasis | PortLinkSpeed | MaxPayload |
  48         // DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd |
  49         // NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 |
  50         // NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 |
  51         // NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride
  52         { PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
  53                 NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
  54                 0x16, 0x00, 0x03 },
  55         { PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
  56                 NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
  57                 0x16, 0x00, 0x03 },
  58         { PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
  59                 NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
  60                 0x16, 0x00, 0x03 },
  61         { PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
  62                 NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
  63                 0x16, 0x00, 0x03 },
  64         { PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
  65                 NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
  66                 0x16, 0x00, 0x03 },
  67         { PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
  68                 NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
  69                 0x16, 0x00, 0x03 },
  70         { PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
  71                 NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
  72                 0x16, 0x00, 0x03 },
  73         { PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
  74                 NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
  75                 0x16, 0x00, 0x03 },
  76         { PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
  77                 NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
  78                 0x16, 0x00, 0x03 },
  79         { PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
  80                 NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
  81                 0x16, 0x00, 0x03 },
  82         { PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
  83                 NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
  84                 0x16, 0x00, 0x03 },
  85         { PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
  86                 NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
  87                 0x16, 0x00, 0x03 },
  88 };
  89
  90 /*
  91  * Standard Tioga Pass PCH PCIe Port Table
  92  */
  93 static const UPD_PCH_PCIE_PORT tp_pch_pci_port_skt0[] = {
  94         //PortIndex ; ForceEnable ; PortLinkSpeed
  95         { 0x00, 0x00, PcieAuto },
  96         { 0x04, 0x00, PcieAuto },
  97         { 0x05, 0x00, PcieAuto },
  98 };
  99
 100 #endif /* _SKXSP_TP_IIO_H_ */