src/mainboard/asus/p5ql-em/early_init.c

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #include <bootblock_common.h>
   5 #include <device/pnp_ops.h>
   6 #include <console/console.h>
   7 #include <northbridge/intel/x4x/x4x.h>
   8 #include <cpu/x86/msr.h>
   9 #include <cpu/intel/speedstep.h>
  10 #include <cf9_reset.h>
  11 #include <superio/winbond/w83627dhg/w83627dhg.h>
  12 #include <superio/winbond/common/winbond.h>
  13
  14 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
  15 #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
  16
  17 void bootblock_mainboard_early_init(void)
  18 {
  19         winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  20 }
  21
  22 static u8 msr_get_fsb(void)
  23 {
  24         u8 fsbcfg;
  25         msr_t msr;
  26         const u32 eax = cpuid_eax(1);
  27
  28         /* Netburst */
  29         if (((eax >> 8) & 0xf) == 0xf) {
  30                 msr = rdmsr(MSR_EBC_FREQUENCY_ID);
  31                 fsbcfg = (msr.lo >> 16) & 0x7;
  32         } else { /* Intel Core 2 */
  33                 msr = rdmsr(MSR_FSB_FREQ);
  34                 fsbcfg = msr.lo & 0x7;
  35         }
  36
  37         return fsbcfg;
  38 }
  39
  40 /* BSEL MCH straps are not hooked up to the CPU as usual but to the SIO */
  41 static int setup_sio_gpio(void)
  42 {
  43         int need_reset = 0;
  44         u8 reg, old_reg;
  45
  46         u8 bsel = msr_get_fsb();
  47         switch (bsel) {
  48         case 0:
  49         case 2:
  50         case 4:
  51                 break;
  52         default:
  53                 printk(BIOS_WARNING,
  54                        "BSEL: Unsupported FSB frequency, using 800MHz\n");
  55                 bsel = 2; /* 800MHz */
  56                 break;
  57         }
  58
  59         pnp_enter_ext_func_mode(GPIO_DEV);
  60         pnp_set_logical_device(GPIO_DEV);
  61
  62         /*
  63          * P5QL-EM:
  64          * BSEL0 -> not hooked up (not supported anyways)
  65          * BSEL1 -> GPIO33 (inverted)
  66          * BSEL2 -> GPIO40
  67          */
  68         reg = 0x92;
  69         /* Multi-function Pin Selection */
  70         old_reg = pnp_read_config(GPIO_DEV, 0x2c);
  71         pnp_write_config(GPIO_DEV, 0x2c, reg);
  72         need_reset = (reg != old_reg);
  73
  74         pnp_write_config(GPIO_DEV, 0x30, 0x0e); /* Enable GPIO3x,4x,5x */
  75         pnp_write_config(GPIO_DEV, 0xf0, 0xf3); /* GPIO3x direction */
  76         pnp_write_config(GPIO_DEV, 0xf2, 0x08); /* GPIO3x inversion */
  77         pnp_write_config(GPIO_DEV, 0xf4, 0x06); /* GPIO4x direction */
  78
  79         const int gpio33 = (bsel & 2) >> 1;
  80         const int gpio40 = (bsel & 4) >> 2;
  81         reg = (gpio33 << 3);
  82         old_reg = pnp_read_config(GPIO_DEV, 0xf1); /* GPIO3x data */
  83         /* Set GPIO32 high like vendor firmware */
  84         pnp_write_config(GPIO_DEV, 0xf1, old_reg | reg | 4);
  85         need_reset += ((reg & 0x8) != (old_reg & 0x8));
  86
  87         reg = gpio40;
  88         old_reg = pnp_read_config(GPIO_DEV, 0xf5); /* GPIO4x data */
  89         pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg);
  90         need_reset += ((reg & 0x1) != (old_reg & 0x1));
  91         pnp_exit_ext_func_mode(GPIO_DEV);
  92
  93         return need_reset;
  94 }
  95
  96 void mb_pre_raminit_setup(int s3_resume)
  97 {
  98         if (!s3_resume && setup_sio_gpio()) {
  99                 printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n");
 100                 full_reset();
 101         }
 102 }
 103
 104 void mb_get_spd_map(u8 spd_map[4])
 105 {
 106         /* This board has first dimm slot of each channel hooked up to
 107            rank0 and rank1, while the second dimm slot is only connected
 108            to rank1. The raminit does not support such setups. So only the
 109            first dimms of each channel are used. */
 110         spd_map[0] = 0x50;
 111         spd_map[2] = 0x52;
 112 }