src/include/spd.h

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 /*
   5  * Serial Presence Detect (SPD) data stored on SDRAM modules.
   6  *
   7  * Datasheet:
   8  *   - Name: PC SDRAM Serial Presence Detect (SPD) Specification
   9  *           Revision 1.2A, December, 1997
  10  *   - PDF: http://www.intel.com/design/chipsets/memory/spdsd12a.pdf
  11  *
  12  * Datasheet (alternative):
  13  *   - Name: SERIAL PRESENCE DETECT STANDARD, General Standard
  14  *           JEDEC Standard No. 21-C
  15  *     Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3):
  16  *   - PDF: http://www.jedec.org/download/search/4_01_02_10R17.pdf
  17  */
  18
  19 #ifndef _SPD_H_
  20 #define _SPD_H_
  21
  22 /* Byte numbers. */
  23 /* Number of bytes used by module manufacturer */
  24 #define SPD_NUM_MANUFACTURER_BYTES          0
  25 #define SPD_TOTAL_SPD_MEMORY_SIZE           1  /* Total SPD memory size */
  26 #define SPD_MEMORY_TYPE                     2  /* (Fundamental) memory type */
  27 #define SPD_NUM_ROWS                        3  /* Number of row address bits */
  28 /* Number of column address bits */
  29 #define SPD_NUM_COLUMNS                     4
  30 /* Number of module rows (banks) */
  31 #define SPD_NUM_DIMM_BANKS                  5
  32 #define SPD_MODULE_DATA_WIDTH_LSB           6  /* Module data width (LSB) */
  33 #define SPD_MODULE_DATA_WIDTH_MSB           7  /* Module data width (MSB) */
  34 /* Module interface signal levels */
  35 #define SPD_MODULE_VOLTAGE                  8
  36 /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
  37 #define SPD_MIN_CYCLE_TIME_AT_CAS_MAX       9
  38 /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac,
  39  * tCAC)
  40  */
  41 #define SPD_ACCESS_TIME_FROM_CLOCK          10
  42 #define SPD_DIMM_CONFIG_TYPE                11 /* Module configuration type */
  43 #define SPD_REFRESH                         12 /* Refresh rate/type */
  44 #define SPD_PRIMARY_SDRAM_WIDTH             13 /* SDRAM width (primary SDRAM) */
  45 /* Error checking SDRAM (data) width */
  46 #define SPD_ERROR_CHECKING_SDRAM_WIDTH      14
  47 /* SDRAM device attributes, minimum clock delay for back to back random
  48  * column
  49  */
  50 #define SPD_MIN_CLOCK_DELAY_B2B_RAND_COLUMN 15
  51 /* SDRAM device attributes, burst lengths supported */
  52 #define SPD_SUPPORTED_BURST_LENGTHS         16
  53 /* SDRAM device attributes, number of banks on SDRAM device */
  54 #define SPD_NUM_BANKS_PER_SDRAM             17
  55 /* SDRAM device attributes, CAS latency */
  56 #define SPD_ACCEPTABLE_CAS_LATENCIES        18
  57 /* SDRAM device attributes, CS latency */
  58 #define SPD_CS_LATENCY                      19
  59 /* SDRAM device attributes, WE latency */
  60 #define SPD_WE_LATENCY                      20
  61 #define SPD_MODULE_ATTRIBUTES               21 /* SDRAM module attributes */
  62 /* SDRAM device attributes, general */
  63 #define SPD_DEVICE_ATTRIBUTES_GENERAL       22
  64 /* SDRAM cycle time (2nd highest CAS latency) */
  65 #define SPD_SDRAM_CYCLE_TIME_2ND            23
  66 /* SDRAM access from clock (2nd highest CAS latency) */
  67 #define SPD_ACCESS_TIME_FROM_CLOCK_2ND      24
  68 /* SDRAM cycle time (3rd highest CAS latency) */
  69 #define SPD_SDRAM_CYCLE_TIME_3RD            25
  70 /* SDRAM access from clock (3rd highest CAS latency) */
  71 #define SPD_ACCESS_TIME_FROM_CLOCK_3RD      26
  72 /* Minimum row precharge time (Trp) */
  73 #define SPD_MIN_ROW_PRECHARGE_TIME          27
  74 /* Minimum row active to row active (Trrd) */
  75 #define SPD_MIN_ROWACTIVE_TO_ROWACTIVE      28
  76 /* Minimum RAS to CAS delay (Trcd) */
  77 #define SPD_MIN_RAS_TO_CAS_DELAY            29
  78 /* Minimum RAS pulse width (Tras) */
  79 #define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY   30
  80 /* Density of each row on module */
  81 #define SPD_DENSITY_OF_EACH_ROW_ON_MODULE   31
  82 /* Command and address signal input setup time */
  83 #define SPD_CMD_SIGNAL_INPUT_SETUP_TIME     32
  84 /* Command and address signal input hold time */
  85 #define SPD_CMD_SIGNAL_INPUT_HOLD_TIME      33
  86 /* Data signal input setup time */
  87 #define SPD_DATA_SIGNAL_INPUT_SETUP_TIME    34
  88 #define SPD_DATA_SIGNAL_INPUT_HOLD_TIME     35 /* Data signal input hold time */
  89 #define SPD_WRITE_RECOVERY_TIME             36 /* Write recovery time (tWR) */
  90 /* Internal write to read command delay (tWTR) */
  91 #define SPD_INT_WRITE_TO_READ_DELAY         37
  92 /* Internal read to precharge command delay (tRTP) */
  93 #define SPD_INT_READ_TO_PRECHARGE_DELAY     38
  94 /* Memory analysis probe characteristics */
  95 #define SPD_MEM_ANALYSIS_PROBE_PARAMS       39
  96 /* Extension of byte 41 (tRC) and byte 42 (tRFC) */
  97 #define SPD_BYTE_41_42_EXTENSION            40
  98 /* Minimum active to active auto refresh (tRCmin) */
  99 #define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH     41
 100 /* Minimum auto refresh to active/auto refresh (tRFC) */
 101 #define SPD_MIN_AUTO_REFRESH_TO_ACT         42
 102 /* Maximum device cycle time (tCKmax) */
 103 #define SPD_MAX_DEVICE_CYCLE_TIME           43
 104 /* Maximum skew between DQS and DQ (tDQSQ) */
 105 #define SPD_MAX_DQS_DQ_SKEW                 44
 106 /* Maximum read data-hold skew factor (tQHS) */
 107 #define SPD_MAX_READ_DATAHOLD_SKEW          45
 108 #define SPD_PLL_RELOCK_TIME                 46 /* PLL relock time */
 109 #define SPD_SPD_DATA_REVISION_CODE          62 /* SPD data revision code */
 110 #define SPD_CHECKSUM_FOR_BYTES_0_TO_62      63 /* Checksum for bytes 0-62 */
 111 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */
 112 #define SPD_MANUFACTURER_JEDEC_ID_CODE      64
 113 #define SPD_MANUFACTURING_LOCATION          72 /* Manufacturing location */
 114 /* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */
 115 #define SPD_MANUFACTURER_PART_NUMBER        73
 116 #define SPD_REVISION_CODE                   91 /* Revision code (bytes 91-92) */
 117 /* Manufacturing date (byte 93: year, byte 94: week) */
 118 #define SPD_MANUFACTURING_DATE              93
 119 /* Assembly serial number (bytes 95-98) */
 120 #define SPD_ASSEMBLY_SERIAL_NUMBER          95
 121 /* Manufacturer specific data (bytes 99-125) */
 122 #define SPD_MANUFACTURER_SPECIFIC_DATA      99
 123 /* Intel specification for frequency */
 124 #define SPD_INTEL_SPEC_FOR_FREQUENCY       126
 125 /* Intel specification details for 100MHz support */
 126 #define SPD_INTEL_SPEC_100_MHZ             127
 127
 128 /* DRAM specifications use the following naming conventions for SPD locations */
 129 #define SPD_tRP                             SPD_MIN_ROW_PRECHARGE_TIME
 130 #define SPD_tRRD                            SPD_MIN_ROWACTIVE_TO_ROWACTIVE
 131 #define SPD_tRCD                            SPD_MIN_RAS_TO_CAS_DELAY
 132 #define SPD_tRAS                            SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY
 133 #define SPD_BANK_DENSITY                    SPD_DENSITY_OF_EACH_ROW_ON_MODULE
 134 #define SPD_ADDRESS_CMD_HOLD                SPD_CMD_SIGNAL_INPUT_HOLD_TIME
 135 /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
 136 #define SPD_tRC                             41
 137 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
 138 #define SPD_tRFC                            42
 139
 140
 141 /* SPD_MEMORY_TYPE values. */
 142 enum spd_memory_type {
 143         SPD_MEMORY_TYPE_UNDEFINED               = 0x00,
 144         SPD_MEMORY_TYPE_FPM_DRAM                = 0x01,
 145         SPD_MEMORY_TYPE_EDO                     = 0x02,
 146         SPD_MEMORY_TYPE_PIPELINED_NIBBLE        = 0x03,
 147         SPD_MEMORY_TYPE_SDRAM                   = 0x04,
 148         SPD_MEMORY_TYPE_MULTIPLEXED_ROM         = 0x05,
 149         SPD_MEMORY_TYPE_SGRAM_DDR               = 0x06,
 150         SPD_MEMORY_TYPE_SDRAM_DDR               = 0x07,
 151         SPD_MEMORY_TYPE_SDRAM_DDR2              = 0x08,
 152         SPD_MEMORY_TYPE_FBDIMM_DDR2             = 0x09,
 153         SPD_MEMORY_TYPE_FB_PROBE_DDR2           = 0x0a,
 154         SPD_MEMORY_TYPE_SDRAM_DDR3              = 0x0b,
 155         SPD_MEMORY_TYPE_DDR4_SDRAM              = 0x0c,
 156         SPD_MEMORY_TYPE_DDR4E_SDRAM             = 0x0e,
 157         SPD_MEMORY_TYPE_LPDDR3_SDRAM            = 0x0f,
 158         SPD_MEMORY_TYPE_LPDDR4_SDRAM            = 0x10,
 159 };
 160
 161 /* SPD_MODULE_VOLTAGE values. */
 162 #define SPD_VOLTAGE_TTL                  0 /* 5.0 Volt/TTL */
 163 #define SPD_VOLTAGE_LVTTL                1 /* LVTTL */
 164 #define SPD_VOLTAGE_HSTL                 2 /* HSTL 1.5 */
 165 #define SPD_VOLTAGE_SSTL3                3 /* SSTL 3.3 */
 166 #define SPD_VOLTAGE_SSTL2                4 /* SSTL 2.5 */
 167 #define SPD_VOLTAGE_SSTL1                5 /* SSTL 1.8 */
 168
 169 /* SPD_DIMM_CONFIG_TYPE values. */
 170 #define ERROR_SCHEME_NONE                0
 171 #define ERROR_SCHEME_PARITY              1
 172 #define ERROR_SCHEME_ECC                 2
 173
 174 /* SPD_ACCEPTABLE_CAS_LATENCIES values. */
 175 // TODO: Check values.
 176 #define SPD_CAS_LATENCY_1_0              0x01
 177 #define SPD_CAS_LATENCY_1_5              0x02
 178 #define SPD_CAS_LATENCY_2_0              0x04
 179 #define SPD_CAS_LATENCY_2_5              0x08
 180 #define SPD_CAS_LATENCY_3_0              0x10
 181 #define SPD_CAS_LATENCY_3_5              0x20
 182 #define SPD_CAS_LATENCY_4_0              0x40
 183
 184 #define SPD_CAS_LATENCY_DDR2_2          (1 << 2)
 185 #define SPD_CAS_LATENCY_DDR2_3          (1 << 3)
 186 #define SPD_CAS_LATENCY_DDR2_4          (1 << 4)
 187 #define SPD_CAS_LATENCY_DDR2_5          (1 << 5)
 188 #define SPD_CAS_LATENCY_DDR2_6          (1 << 6)
 189 #define SPD_CAS_LATENCY_DDR2_7          (1 << 7)
 190
 191 /* SPD_SUPPORTED_BURST_LENGTHS values. */
 192 #define SPD_BURST_LENGTH_1               1
 193 #define SPD_BURST_LENGTH_2               2
 194 #define SPD_BURST_LENGTH_4               4
 195 #define SPD_BURST_LENGTH_8               8
 196 #define SPD_BURST_LENGTH_PAGE            (1 << 7)
 197
 198 /* SPD_MODULE_ATTRIBUTES values. */
 199 #define MODULE_BUFFERED                  1
 200 #define MODULE_REGISTERED                2
 201
 202 /* DIMM SPD addresses */
 203 #define DIMM0                            0x50
 204 #define DIMM1                            0x51
 205 #define DIMM2                            0x52
 206 #define DIMM3                            0x53
 207 #define DIMM4                            0x54
 208 #define DIMM5                            0x55
 209 #define DIMM6                            0x56
 210 #define DIMM7                            0x57
 211
 212 #define RC00 0
 213 #define RC01 1
 214 #define RC02 2
 215 #define RC03 3
 216 #define RC04 4
 217 #define RC05 5
 218 #define RC06 6
 219 #define RC07 7
 220 #define RC08 8
 221 #define RC09 9
 222 #define RC10 10
 223 #define RC11 11
 224 #define RC12 12
 225 #define RC13 13
 226 #define RC14 14
 227 #define RC15 15
 228 #define RC16 16
 229 #define RC17 17
 230 #define RC18 18
 231 #define RC19 19
 232 #define RC20 20
 233 #define RC21 21
 234 #define RC22 22
 235 #define RC23 23
 236 #define RC24 24
 237 #define RC25 25
 238 #define RC26 26
 239 #define RC27 27
 240 #define RC28 28
 241 #define RC29 29
 242 #define RC30 30
 243 #define RC31 31
 244
 245 #define RC32 32
 246 #define RC33 33
 247 #define RC34 34
 248 #define RC35 35
 249 #define RC36 36
 250 #define RC37 37
 251 #define RC38 38
 252 #define RC39 39
 253 #define RC40 40
 254 #define RC41 41
 255 #define RC42 42
 256 #define RC43 43
 257 #define RC44 44
 258 #define RC45 45
 259 #define RC46 46
 260 #define RC47 47
 261 #define RC48 48
 262 #define RC49 49
 263 #define RC50 50
 264 #define RC51 51
 265 #define RC52 52
 266 #define RC53 53
 267 #define RC54 54
 268 #define RC55 55
 269 #define RC56 56
 270 #define RC57 57
 271 #define RC58 58
 272 #define RC59 59
 273 #define RC60 60
 274 #define RC61 61
 275 #define RC62 62
 276 #define RC63 63
 277
 278 /* Byte 3: Module type information */
 279 #define SPD_UNDEFINED 0x00
 280 #define SPD_RDIMM 0x01
 281 #define SPD_UDIMM 0x02
 282 #define SPD_SODIMM 0x04
 283 #define SPD_72B_SO_CDIMM 0x06
 284 #define SPD_72B_SO_RDIMM 0x07
 285 #define SPD_MICRO_DIMM 0x08
 286 #define SPD_MINI_RDIMM 0x10
 287 #define SPD_MINI_UDIMM 0x20
 288
 289 #define SPD_ECC_8BIT (1<<3)
 290
 291 #endif