1 /* This file is part of the coreboot project. */
2 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <commonlib/helpers.h>
10 /* IGD PCI Configuration register */
11 #define ASLS 0xfc /* OpRegion Base */
12 #define SWSCI 0xe8 /* SWSCI Register */
13 #define SWSMISCI 0xe0 /* SWSMISCI Register */
14 #define GSSCIE (1 << 0) /* SCI Event trigger */
15 #define SMISCISEL (1 << 15) /* Select SMI or SCI event source */
17 /* mailbox 0: header */
19 u8 signature
[16]; /* Offset 0 OpRegion signature */
20 u32 size
; /* Offset 16 OpRegion size */
21 u32 version
; /* Offset 20 OpRegion structure version */
22 u8 sbios_version
[32]; /* Offset 24 System BIOS build version */
23 u8 vbios_version
[16]; /* Offset 56 Video BIOS build version */
24 u8 driver_version
[16]; /* Offset 72 Graphic drvr build version */
25 u32 mailboxes
; /* Offset 88 Mailboxes supported */
26 u32 dmod
; /* Offset 92 Driver Model */
27 u32 pcon
; /* Offset 96 Platform Capabilities */
28 u16 dver
[16]; /* Offset 100 GOP Version */
29 u8 reserved
[124]; /* Offset 132 Reserved */
30 } __packed opregion_header_t
;
32 #define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
33 #define IGD_OPREGION_VERSION 2
35 #define IGD_MBOX1 (1 << 0)
36 #define IGD_MBOX2 (1 << 1)
37 #define IGD_MBOX3 (1 << 2)
38 #define IGD_MBOX4 (1 << 3)
39 #define IGD_MBOX5 (1 << 4)
41 #define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
42 IGD_MBOX4 | IGD_MBOX5)
43 #define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
45 #define SBIOS_VERSION_SIZE 32
47 /* mailbox 1: public ACPI methods */
49 u32 drdy
; /* Offset 0 Driver readiness */
50 u32 csts
; /* Offset 4 Status */
51 u32 cevt
; /* Offset 8 Current event */
52 u8 reserved
[20]; /* Offset 12 Reserved */
53 u32 didl
; /* Offset 32 Supported display device 1 */
54 u32 ddl2
; /* Offset 36 Supported display device 2 */
55 u32 ddl3
; /* Offset 40 Supported display device 3 */
56 u32 ddl4
; /* Offset 44 Supported display device 4 */
57 u32 ddl5
; /* Offset 48 Supported display device 5 */
58 u32 ddl6
; /* Offset 52 Supported display device 6 */
59 u32 ddl7
; /* Offset 56 Supported display device 7 */
60 u32 ddl8
; /* Offset 60 Supported display device 8 */
61 u32 cpdl
; /* Offset 64 Currently present display device 1 */
62 u32 cpl2
; /* Offset 68 Currently present display device 2 */
63 u32 cpl3
; /* Offset 72 Currently present display device 3 */
64 u32 cpl4
; /* Offset 76 Currently present display device 4 */
65 u32 cpl5
; /* Offset 80 Currently present display device 5 */
66 u32 cpl6
; /* Offset 84 Currently present display device 6 */
67 u32 cpl7
; /* Offset 88 Currently present display device 7 */
68 u32 cpl8
; /* Offset 92 Currently present display device 8 */
69 u32 cadl
; /* Offset 96 Currently active display device 1 */
70 u32 cal2
; /* Offset 100 Currently active display device 2 */
71 u32 cal3
; /* Offset 104 Currently active display device 3 */
72 u32 cal4
; /* Offset 108 Currently active display device 4 */
73 u32 cal5
; /* Offset 112 Currently active display device 5 */
74 u32 cal6
; /* Offset 116 Currently active display device 6 */
75 u32 cal7
; /* Offset 120 Currently active display device 7 */
76 u32 cal8
; /* Offset 124 Currently active display device 8 */
77 u32 nadl
; /* Offset 128 Next active device 1 */
78 u32 ndl2
; /* Offset 132 Next active device 2 */
79 u32 ndl3
; /* Offset 136 Next active device 3 */
80 u32 ndl4
; /* Offset 140 Next active device 4 */
81 u32 ndl5
; /* Offset 144 Next active device 5 */
82 u32 ndl6
; /* Offset 148 Next active device 6 */
83 u32 ndl7
; /* Offset 152 Next active device 7 */
84 u32 ndl8
; /* Offset 156 Next active device 8 */
85 u32 aslp
; /* Offset 160 ASL sleep timeout */
86 u32 tidx
; /* Offset 164 Toggle table index */
87 u32 chpd
; /* Offset 168 Current hot plug enable indicator */
88 u32 clid
; /* Offset 172 Current lid state indicator */
89 u32 cdck
; /* Offset 176 Current docking state indicator */
90 u32 sxsw
; /* Offset 180 Display Switch notification on Sx State
93 u32 evts
; /* Offset 184 Events supported by ASL */
94 u32 cnot
; /* Offset 188 Current OS Notification */
95 u32 nrdy
; /* Offset 192 Reasons for DRDY = 0 */
96 u32 ddl9
; /* Offset 196 Extended Supported display device 1 */
97 u32 dd10
; /* Offset 200 Extended Supported display device 2 */
98 u32 dd11
; /* Offset 204 Extended Supported display device 3 */
99 u32 dd12
; /* Offset 208 Extended Supported display device 4 */
100 u32 dd13
; /* Offset 212 Extended Supported display device 5 */
101 u32 dd14
; /* Offset 216 Extended Supported display device 6 */
102 u32 dd15
; /* Offset 220 Extended Supported display device 7 */
103 u32 cpl9
; /* Offset 224 Extended Currently present device 1 */
104 u32 cp10
; /* Offset 228 Extended Currently present device 2 */
105 u32 cp11
; /* Offset 232 Extended Currently present device 3 */
106 u32 cp12
; /* Offset 236 Extended Currently present device 4 */
107 u32 cp13
; /* Offset 240 Extended Currently present device 5 */
108 u32 cp14
; /* Offset 244 Extended Currently present device 6 */
109 u32 cp15
; /* Offset 248 Extended Currently present device 7 */
110 u8 reserved2
[4]; /* Offset 252 Reserved 4 bytes */
111 } __packed opregion_mailbox1_t
;
113 /* mailbox 2: software sci interface */
115 u32 scic
; /* Offset 0 Software SCI function number parameters */
116 u32 parm
; /* Offset 4 Software SCI function number parameters */
117 u32 dslp
; /* Offset 8 Driver sleep timeout */
118 u8 reserved
[244]; /* Offset 12 Reserved */
119 } __packed opregion_mailbox2_t
;
121 /* mailbox 3: power conservation */
123 u32 ardy
; /* Offset 0 Driver readiness */
124 u32 aslc
; /* Offset 4 ASLE interrupt command / status */
125 u32 tche
; /* Offset 8 Technology enabled indicator */
126 u32 alsi
; /* Offset 12 Current ALS illuminance reading */
127 u32 bclp
; /* Offset 16 Backlight britness to set */
128 u32 pfit
; /* Offset 20 Panel fitting Request */
129 u32 cblv
; /* Offset 24 Brightness Current State */
130 u16 bclm
[20]; /* Offset 28 Backlight Brightness Level Duty
131 * Cycle Mapping Table
133 u32 cpfm
; /* Offset 68 Panel Fitting Current Mode */
134 u32 epfm
; /* Offset 72 Enabled Panel Fitting Modes */
135 u8 plut
[74]; /* Offset 76 Panel Look Up Table */
136 u32 pfmb
; /* Offset 150 PWM Frequency and Minimum
139 u32 ccdv
; /* Offset 154 Color Correction Default Values */
140 u32 pcft
; /* Offset 158 Power Conservation Features */
141 u32 srot
; /* Offset 162 Supported Rotation angle */
142 u32 iuer
; /* Offset 166 Intel Ultrabook Event Register */
143 u64 fdsp
; /* Offset 170 FFS Display Physical address */
144 u32 fdss
; /* Offset 178 FFS Display Size */
145 u32 stat
; /* Offset 182 State Indicator */
146 u64 rvda
; /* Offset 186 (Igd opregion offset 0x3BAh)
147 * Physical address of Raw VBT data
149 u32 rvds
; /* Offset 194 (Igd opregion offset 0x3C2h)
150 * Size of Raw VBT data
152 u8 reserved
[58]; /* Offset 198 Reserved */
153 } __packed opregion_mailbox3_t
;
155 #define IGD_BACKLIGHT_BRIGHTNESS 0xff
156 #define IGD_INITIAL_BRIGHTNESS 0x64
158 #define IGD_FIELD_VALID (1UL << 31)
159 #define IGD_WORD_FIELD_VALID (1 << 15)
160 #define IGD_PFIT_STRETCH 6
165 } __packed opregion_vbt_t
;
167 /* Mailbox 5: BIOS to Driver Notification Extension */
169 u32 phed
; /* Offset 7168 Panel Header */
170 u8 bddc
[256]; /* Offset 7172 Panel EDID */
171 u8 reserved
[764]; /* Offset 7428 764 bytes */
172 } __packed opregion_mailbox5_t
;
176 opregion_header_t header
;
177 opregion_mailbox1_t mailbox1
;
178 opregion_mailbox2_t mailbox2
;
179 opregion_mailbox3_t mailbox3
;
181 opregion_mailbox5_t mailbox5
;
183 } __packed igd_opregion_t
;
185 /* Intel Video BIOS (Option ROM) */
192 } __packed optionrom_header_t
;
194 #define OPROM_SIGNATURE 0xaa55
209 } __packed optionrom_pcir_t
;
212 u8 hdr_signature
[20];
218 u32 hdr_vbt_datablock
;
220 u8 datahdr_signature
[16];
223 u16 datahdr_datablocksize
;
226 u16 coreblock_biossize
;
227 u8 coreblock_biostype
;
228 u8 coreblock_releasestatus
;
229 u8 coreblock_hwsupported
;
230 u8 coreblock_integratedhw
;
231 u8 coreblock_biosbuild
[4];
232 u8 coreblock_biossignon
[155];
233 } __packed optionrom_vbt_t
;
235 void intel_gma_opregion_register(uintptr_t opregion
);
236 void intel_gma_restore_opregion(void);
237 uintptr_t gma_get_gnvs_aslb(const void *gnvs
);
238 void gma_set_gnvs_aslb(void *gnvs
, uintptr_t aslb
);
239 enum cb_err
intel_gma_init_igd_opregion(igd_opregion_t
*opregion
);
242 * Returns the CBFS filename of the VBT blob.
244 * The default implementation returns "vbt.bin", but other implementations can
247 const char *mainboard_vbt_filename(void);
250 * locate vbt.bin file. Returns a pointer to its content.
251 * If vbt_size is non-NULL, also return the vbt's size.
253 void *locate_vbt(size_t *vbt_size
);
255 #endif /* _COMMON_GMA_H_ */