src/drivers/intel/fsp2_0/util.c

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #include <device/mmio.h>
   5 #include <cf9_reset.h>
   6 #include <console/console.h>
   7 #include <fsp/util.h>
   8 #include <string.h>
   9 #include <types.h>
  10
  11 static bool looks_like_fsp_header(const uint8_t *raw_hdr)
  12 {
  13         if (memcmp(raw_hdr, FSP_HDR_SIGNATURE, 4)) {
  14                 printk(BIOS_ALERT, "Did not find a valid FSP signature\n");
  15                 return false;
  16         }
  17
  18         if (read32(raw_hdr + 4) != FSP_HDR_LEN) {
  19                 printk(BIOS_ALERT, "FSP header has invalid length\n");
  20                 return false;
  21         }
  22
  23         return true;
  24 }
  25
  26 enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob)
  27 {
  28         const uint8_t *raw_hdr = fsp_blob;
  29
  30         if (!looks_like_fsp_header(raw_hdr))
  31                 return CB_ERR;
  32
  33         hdr->spec_version = read8(raw_hdr + 10);
  34         hdr->revision = read8(raw_hdr + 11);
  35         hdr->fsp_revision = read32(raw_hdr + 12);
  36         memcpy(hdr->image_id, raw_hdr + 16, ARRAY_SIZE(hdr->image_id));
  37         hdr->image_id[ARRAY_SIZE(hdr->image_id) - 1] = '\0';
  38         hdr->image_size = read32(raw_hdr + 24);
  39         hdr->image_base = read32(raw_hdr + 28);
  40         hdr->image_attribute = read16(raw_hdr + 32);
  41         hdr->component_attribute = read16(raw_hdr + 34);
  42         hdr->cfg_region_offset = read32(raw_hdr + 36);
  43         hdr->cfg_region_size = read32(raw_hdr + 40);
  44         hdr->temp_ram_init_entry = read32(raw_hdr + 48);
  45         hdr->temp_ram_exit_entry = read32(raw_hdr + 64);
  46         hdr->notify_phase_entry_offset = read32(raw_hdr + 56);
  47         hdr->memory_init_entry_offset = read32(raw_hdr + 60);
  48         hdr->silicon_init_entry_offset = read32(raw_hdr + 68);
  49
  50         return CB_SUCCESS;
  51 }
  52
  53 enum cb_err fsp_validate_component(struct fsp_header *hdr,
  54                                         const struct region_device *rdev)
  55 {
  56         void *membase;
  57
  58         /* Map just enough of the file to be able to parse the header. */
  59         membase = rdev_mmap(rdev, FSP_HDR_OFFSET, FSP_HDR_LEN);
  60
  61         if (membase == NULL) {
  62                 printk(BIOS_CRIT, "Could not mmap() FSP header.\n");
  63                 return CB_ERR;
  64         }
  65
  66         if (fsp_identify(hdr, membase) != CB_SUCCESS) {
  67                 rdev_munmap(rdev, membase);
  68                 printk(BIOS_CRIT, "No valid FSP header\n");
  69                 return CB_ERR;
  70         }
  71
  72         rdev_munmap(rdev, membase);
  73
  74         if (CONFIG(DISPLAY_FSP_HEADER))
  75                 fsp_print_header_info(hdr);
  76
  77         /* Check if size specified in the header matches the cbfs file size */
  78         if (region_device_sz(rdev) < hdr->image_size) {
  79                 printk(BIOS_CRIT, "Component size bigger than cbfs file.\n");
  80                 return CB_ERR;
  81         }
  82
  83         return CB_SUCCESS;
  84 }
  85
  86 static bool fsp_reset_requested(uint32_t status)
  87 {
  88         return (status >= FSP_STATUS_RESET_REQUIRED_COLD &&
  89                 status <= FSP_STATUS_RESET_REQUIRED_8);
  90 }
  91
  92 void fsp_handle_reset(uint32_t status)
  93 {
  94         if (!fsp_reset_requested(status))
  95                 return;
  96
  97         printk(BIOS_SPEW, "FSP: handling reset type %x\n", status);
  98
  99         switch (status) {
 100         case FSP_STATUS_RESET_REQUIRED_COLD:
 101                 full_reset();
 102                 break;
 103         case FSP_STATUS_RESET_REQUIRED_WARM:
 104                 system_reset();
 105                 break;
 106         case FSP_STATUS_RESET_REQUIRED_3:
 107         case FSP_STATUS_RESET_REQUIRED_4:
 108         case FSP_STATUS_RESET_REQUIRED_5:
 109         case FSP_STATUS_RESET_REQUIRED_6:
 110         case FSP_STATUS_RESET_REQUIRED_7:
 111         case FSP_STATUS_RESET_REQUIRED_8:
 112                 chipset_handle_reset(status);
 113                 break;
 114         default:
 115                 break;
 116         }
 117 }