1 /* This file is part of the coreboot project. */
2 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 #include <security/vboot/antirollback.h>
5 #include <arch/symbols.h>
10 #include <cf9_reset.h>
11 #include <console/console.h>
16 #include <mrc_cache.h>
17 #include <program_loading.h>
18 #include <romstage_handoff.h>
21 #include <timestamp.h>
22 #include <security/vboot/vboot_common.h>
23 #include <security/tpm/tspi.h>
25 #include <fsp/memory_init.h>
28 static uint8_t temp_ram
[CONFIG_FSP_TEMP_RAM_SIZE
] __aligned(sizeof(uint64_t));
30 /* TPM MRC hash functionality depends on vboot starting before memory init. */
31 _Static_assert(!CONFIG(FSP2_0_USES_TPM_MRC_HASH
) ||
32 CONFIG(VBOOT_STARTS_IN_BOOTBLOCK
),
33 "for TPM MRC hash functionality, vboot must start in bootblock");
35 static void save_memory_training_data(bool s3wake
, uint32_t fsp_version
)
40 if (!CONFIG(CACHE_MRC_SETTINGS
) || s3wake
)
43 mrc_data
= fsp_find_nv_storage_data(&mrc_data_size
);
45 printk(BIOS_ERR
, "Couldn't find memory training data HOB.\n");
50 * Save MRC Data to CBMEM. By always saving the data this forces
51 * a retrain after a trip through Chrome OS recovery path. The
52 * code which saves the data to flash doesn't write if the latest
53 * training data matches this one.
55 if (mrc_cache_stash_data(MRC_TRAINING_DATA
, fsp_version
, mrc_data
,
57 printk(BIOS_ERR
, "Failed to stash MRC data\n");
59 if (CONFIG(FSP2_0_USES_TPM_MRC_HASH
))
60 mrc_cache_update_hash(mrc_data
, mrc_data_size
);
63 static void do_fsp_post_memory_init(bool s3wake
, uint32_t fsp_version
)
65 struct range_entry fsp_mem
;
67 fsp_find_reserved_memory(&fsp_mem
);
69 /* initialize cbmem by adding FSP reserved memory first thing */
71 cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY
,
72 range_entry_size(&fsp_mem
));
73 } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY
,
74 range_entry_size(&fsp_mem
))) {
75 if (CONFIG(HAVE_ACPI_RESUME
)) {
77 "Failed to recover CBMEM in S3 resume.\n");
78 /* Failed S3 resume, reset to come up cleanly */
79 /* FIXME: A "system" reset is likely enough: */
84 /* make sure FSP memory is reserved in cbmem */
85 if (range_entry_base(&fsp_mem
) !=
86 (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY
))
87 die("Failed to accommodate FSP reserved memory request!\n");
89 save_memory_training_data(s3wake
, fsp_version
);
91 /* Create romstage handof information */
92 romstage_handoff_init(s3wake
);
95 static void fsp_fill_mrc_cache(FSPM_ARCH_UPD
*arch_upd
, uint32_t fsp_version
)
97 struct region_device rdev
;
100 arch_upd
->NvsBufferPtr
= NULL
;
102 if (!CONFIG(CACHE_MRC_SETTINGS
))
106 * In recovery mode, force retraining:
107 * 1. Recovery cache is not supported, or
108 * 2. Memory retrain switch is set.
110 if (vboot_recovery_mode_enabled()) {
111 if (!CONFIG(HAS_RECOVERY_MRC_CACHE
))
113 if (get_recovery_mode_retrain_switch())
117 if (mrc_cache_get_current(MRC_TRAINING_DATA
, fsp_version
, &rdev
) < 0)
120 /* Assume boot device is memory mapped. */
121 assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED
));
122 data
= rdev_mmap_full(&rdev
);
127 if (CONFIG(FSP2_0_USES_TPM_MRC_HASH
) &&
128 !mrc_cache_verify_hash(data
, region_device_sz(&rdev
)))
131 /* MRC cache found */
132 arch_upd
->NvsBufferPtr
= data
;
134 printk(BIOS_SPEW
, "MRC cache found, size %zx\n",
135 region_device_sz(&rdev
));
138 static enum cb_err
check_region_overlap(const struct memranges
*ranges
,
139 const char *description
,
140 uintptr_t begin
, uintptr_t end
)
142 const struct range_entry
*r
;
144 memranges_each_entry(r
, ranges
) {
145 if (end
<= range_entry_base(r
))
147 if (begin
>= range_entry_end(r
))
149 printk(BIOS_CRIT
, "'%s' overlaps currently running program: "
150 "[%p, %p)\n", description
, (void *)begin
, (void *)end
);
157 static enum cb_err
setup_fsp_stack_frame(FSPM_ARCH_UPD
*arch_upd
,
158 const struct memranges
*memmap
)
160 uintptr_t stack_begin
;
164 * FSPM_UPD passed here is populated with default values
165 * provided by the blob itself. We let FSPM use top of CAR
166 * region of the size it requests.
168 stack_end
= (uintptr_t)_car_region_end
;
169 stack_begin
= stack_end
- arch_upd
->StackSize
;
170 if (check_region_overlap(memmap
, "FSPM stack", stack_begin
,
171 stack_end
) != CB_SUCCESS
)
174 arch_upd
->StackBase
= (void *)stack_begin
;
178 static enum cb_err
fsp_fill_common_arch_params(FSPM_ARCH_UPD
*arch_upd
,
179 bool s3wake
, uint32_t fsp_version
,
180 const struct memranges
*memmap
)
183 * FSP 2.1 version would use same stack as coreboot instead of
184 * setting up separate stack frame. FSP 2.1 would not relocate stack
185 * top and does not reinitialize stack pointer. The parameters passed
186 * as StackBase and StackSize are actually for temporary RAM and HOBs
187 * and are not related to FSP stack at all.
189 if (CONFIG(FSP_USES_CB_STACK
)) {
190 arch_upd
->StackBase
= temp_ram
;
191 arch_upd
->StackSize
= sizeof(temp_ram
);
192 } else if (setup_fsp_stack_frame(arch_upd
, memmap
)) {
196 fsp_fill_mrc_cache(arch_upd
, fsp_version
);
198 /* Configure bootmode */
201 * For S3 resume case, if valid mrc cache data is not found or
202 * RECOVERY_MRC_CACHE hash verification fails, the S3 data
203 * pointer would be null and S3 resume fails with fsp-m
204 * returning error. Invoking a reset here saves time.
206 if (!arch_upd
->NvsBufferPtr
)
207 /* FIXME: A "system" reset is likely enough: */
209 arch_upd
->BootMode
= FSP_BOOT_ON_S3_RESUME
;
211 if (arch_upd
->NvsBufferPtr
)
213 FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES
;
215 arch_upd
->BootMode
= FSP_BOOT_WITH_FULL_CONFIGURATION
;
218 printk(BIOS_SPEW
, "bootmode is set to: %d\n", arch_upd
->BootMode
);
224 uint8_t fsp_memory_mainboard_version(void)
230 uint8_t fsp_memory_soc_version(void)
236 * Allow SoC and/or mainboard to bump the revision of the FSP setting
237 * number. The FSP spec uses the low 8 bits as the build number. Take over
238 * bits 3:0 for the SoC setting and bits 7:4 for the mainboard. That way
239 * a tweak in the settings will bump the version used to track the cached
240 * setting which triggers retraining when the FSP version hasn't changed, but
241 * the SoC or mainboard settings have.
243 static uint32_t fsp_memory_settings_version(const struct fsp_header
*hdr
)
245 /* Use the full FSP version by default. */
246 uint32_t ver
= hdr
->fsp_revision
;
248 if (!CONFIG(FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
))
252 ver
|= (0xf & fsp_memory_mainboard_version()) << 4;
253 ver
|= (0xf & fsp_memory_soc_version()) << 0;
258 static void do_fsp_memory_init(struct fsp_header
*hdr
, bool s3wake
,
259 const struct memranges
*memmap
)
262 fsp_memory_init_fn fsp_raminit
;
263 FSPM_UPD fspm_upd
, *upd
;
264 FSPM_ARCH_UPD
*arch_upd
;
265 uint32_t fsp_version
;
267 post_code(POST_MEM_PREINIT_PREP_START
);
269 fsp_version
= fsp_memory_settings_version(hdr
);
271 upd
= (FSPM_UPD
*)(hdr
->cfg_region_offset
+ hdr
->image_base
);
273 if (upd
->FspUpdHeader
.Signature
!= FSPM_UPD_SIGNATURE
)
274 die_with_post_code(POST_INVALID_VENDOR_BINARY
,
275 "Invalid FSPM signature!\n");
277 /* Copy the default values from the UPD area */
278 memcpy(&fspm_upd
, upd
, sizeof(fspm_upd
));
280 arch_upd
= &fspm_upd
.FspmArchUpd
;
282 /* Reserve enough memory under TOLUD to save CBMEM header */
283 arch_upd
->BootLoaderTolumSize
= cbmem_overhead_size();
285 /* Fill common settings on behalf of chipset. */
286 if (fsp_fill_common_arch_params(arch_upd
, s3wake
, fsp_version
,
287 memmap
) != CB_SUCCESS
)
288 die_with_post_code(POST_INVALID_VENDOR_BINARY
,
289 "FSPM_ARCH_UPD not found!\n");
291 /* Give SoC and mainboard a chance to update the UPD */
292 platform_fsp_memory_init_params_cb(&fspm_upd
, fsp_version
);
295 setup_mma(&fspm_upd
.FspmConfig
);
297 post_code(POST_MEM_PREINIT_PREP_END
);
299 /* Call FspMemoryInit */
300 fsp_raminit
= (void *)(hdr
->image_base
+ hdr
->memory_init_entry_offset
);
301 fsp_debug_before_memory_init(fsp_raminit
, upd
, &fspm_upd
);
303 post_code(POST_FSP_MEMORY_INIT
);
304 timestamp_add_now(TS_FSP_MEMORY_INIT_START
);
305 status
= fsp_raminit(&fspm_upd
, fsp_get_hob_list_ptr());
306 post_code(POST_FSP_MEMORY_EXIT
);
307 timestamp_add_now(TS_FSP_MEMORY_INIT_END
);
309 /* Handle any errors returned by FspMemoryInit */
310 fsp_handle_reset(status
);
311 if (status
!= FSP_SUCCESS
) {
312 printk(BIOS_CRIT
, "FspMemoryInit returned 0x%08x\n", status
);
313 die_with_post_code(POST_RAM_FAILURE
,
314 "FspMemoryInit returned an error!\n");
317 do_fsp_post_memory_init(s3wake
, fsp_version
);
320 * fsp_debug_after_memory_init() checks whether the end of the tolum
321 * region is the same as the top of cbmem, so must be called here
322 * after cbmem has been initialised in do_fsp_post_memory_init().
324 fsp_debug_after_memory_init(status
);
327 /* Load the binary into the memory specified by the info header. */
328 static enum cb_err
load_fspm_mem(struct fsp_header
*hdr
,
329 const struct region_device
*rdev
,
330 const struct memranges
*memmap
)
332 uintptr_t fspm_begin
;
335 if (fsp_validate_component(hdr
, rdev
) != CB_SUCCESS
)
338 fspm_begin
= hdr
->image_base
;
339 fspm_end
= fspm_begin
+ hdr
->image_size
;
341 if (check_region_overlap(memmap
, "FSPM", fspm_begin
, fspm_end
) !=
345 /* Load binary into memory at provided address. */
346 if (rdev_readat(rdev
, (void *)fspm_begin
, 0, fspm_end
- fspm_begin
) < 0)
352 /* Handle the case when FSPM is running XIP. */
353 static enum cb_err
load_fspm_xip(struct fsp_header
*hdr
,
354 const struct region_device
*rdev
)
358 if (fsp_validate_component(hdr
, rdev
) != CB_SUCCESS
)
361 base
= rdev_mmap_full(rdev
);
362 if ((uintptr_t)base
!= hdr
->image_base
) {
363 printk(BIOS_CRIT
, "FSPM XIP base does not match: %p vs %p\n",
364 (void *)(uintptr_t)hdr
->image_base
, base
);
369 * Since the component is XIP it's already in the address space. Thus,
370 * there's no need to rdev_munmap().
375 void fsp_memory_init(bool s3wake
)
377 struct fsp_header hdr
;
379 struct cbfsf file_desc
;
380 struct region_device file_data
;
381 const char *name
= CONFIG_FSP_M_CBFS
;
382 struct memranges memmap
;
383 struct range_entry prog_ranges
[2];
385 elog_boot_notify(s3wake
);
387 if (cbfs_boot_locate(&file_desc
, name
, NULL
)) {
388 printk(BIOS_CRIT
, "Could not locate %s in CBFS\n", name
);
389 die("FSPM not available!\n");
392 cbfs_file_data(&file_data
, &file_desc
);
394 /* Build up memory map of romstage address space including CAR. */
395 memranges_init_empty(&memmap
, &prog_ranges
[0], ARRAY_SIZE(prog_ranges
));
396 if (ENV_CACHE_AS_RAM
)
397 memranges_insert(&memmap
, (uintptr_t)_car_region_start
,
398 _car_unallocated_start
- _car_region_start
, 0);
399 memranges_insert(&memmap
, (uintptr_t)_program
, REGION_SIZE(program
), 0);
401 if (!CONFIG(FSP_M_XIP
))
402 status
= load_fspm_mem(&hdr
, &file_data
, &memmap
);
404 status
= load_fspm_xip(&hdr
, &file_data
);
406 if (status
!= CB_SUCCESS
)
407 die("Loading FSPM failed!\n");
409 /* Signal that FSP component has been loaded. */
410 prog_segment_loaded(hdr
.image_base
, hdr
.image_size
, SEG_FINAL
);
412 timestamp_add_now(TS_BEFORE_INITRAM
);
414 do_fsp_memory_init(&hdr
, s3wake
, &memmap
);
416 timestamp_add_now(TS_AFTER_INITRAM
);