src/device/dram/ddr2.c

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 /**
   5  * @file ddr2.c
   6  *
   7  * \brief Utilities for decoding DDR2 SPDs
   8  */
   9
  10 #include <console/console.h>
  11 #include <device/device.h>
  12 #include <device/dram/ddr2.h>
  13 #include <lib.h>
  14 #include <string.h>
  15 #include <types.h>
  16
  17 /*==============================================================================
  18  * = DDR2 SPD decoding helpers
  19  *----------------------------------------------------------------------------*/
  20
  21 /**
  22  * \brief Checks if the DIMM is Registered based on byte[20] of the SPD
  23  *
  24  * Tells if the DIMM type is registered or not.
  25  *
  26  * @param type DIMM type. This is byte[20] of the SPD.
  27  */
  28 int spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type)
  29 {
  30         if ((type == SPD_DDR2_DIMM_TYPE_RDIMM)
  31                         || (type == SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM)
  32                         || (type == SPD_DDR2_DIMM_TYPE_MINI_RDIMM))
  33                 return 1;
  34
  35         return 0;
  36 }
  37
  38 /**
  39  * \brief Calculate the checksum of a DDR2 SPD unique identifier
  40  *
  41  * @param spd pointer to raw SPD data
  42  * @param len length of data in SPD
  43  *
  44  * @return the checksum of SPD data bytes 63, or 0 when spd data is truncated.
  45  */
  46 u8 spd_ddr2_calc_checksum(u8 *spd, int len)
  47 {
  48         int i;
  49         u8 c = 0;
  50
  51         if (len < 63)
  52                 /* Not enough bytes available to get the checksum */
  53                 return 0;
  54
  55         for (i = 0; i < 63; i++)
  56                 c += spd[i];
  57
  58         return c;
  59 }
  60
  61 /**
  62  * \brief Calculate the CRC of a DDR2 SPD unique identifier
  63  *
  64  * @param spd pointer to raw SPD data
  65  * @param len length of data in SPD
  66  *
  67  * @return the CRC of SPD data bytes 64..72 and 93..98, or 0
  68  *  when spd data is truncated.
  69  */
  70 u16 spd_ddr2_calc_unique_crc(const u8 *spd, int len)
  71 {
  72         u8 id_bytes[15];
  73         int i, j = 0;
  74         if (len < 98)
  75                 /* Not enough bytes available to get the CRC */
  76                 return 0;
  77         for (i = 64; i <= 72; i++)
  78                 id_bytes[j++] = spd[i];
  79         for (i = 93; i <= 98; i++)
  80                 id_bytes[j++] = spd[i];
  81
  82         return ddr_crc16(id_bytes, 15);
  83 }
  84
  85 /**
  86  * \brief Return size of SPD.
  87  *
  88  * Returns size of SPD. Usually 128 Byte.
  89  */
  90 u32 spd_decode_spd_size_ddr2(u8 byte0)
  91 {
  92         return MIN(byte0, SPD_SIZE_MAX_DDR2);
  93 }
  94
  95 /**
  96  * \brief Return size of eeprom.
  97  *
  98  * Returns size of eeprom. Usually 256 Byte.
  99  */
 100 u32 spd_decode_eeprom_size_ddr2(u8 byte1)
 101 {
 102         if (!byte1)
 103                 return 0;
 104
 105         if (byte1 > 0x0e)
 106                 return 0x3fff;
 107
 108         return 1 << byte1;
 109 }
 110
 111 /**
 112  * \brief Return index of MSB set
 113  *
 114  * Returns the index of MSB set.
 115  */
 116 u8 spd_get_msbs(u8 c)
 117 {
 118         return log2(c);
 119 }
 120
 121 /**
 122  * \brief Decode SPD tck cycle time
 123  *
 124  * Decodes a raw SPD data from a DDR2 DIMM.
 125  * Returns cycle time in 1/256th ns.
 126  */
 127 static int spd_decode_tck_time(u32 *tck, u8 c)
 128 {
 129         u8 high, low;
 130
 131         high = c >> 4;
 132
 133         switch (c & 0xf) {
 134         case 0xa:
 135                 low = 25;
 136                 break;
 137         case 0xb:
 138                 low = 33;
 139                 break;
 140         case 0xc:
 141                 low = 66;
 142                 break;
 143         case 0xd:
 144                 low = 75;
 145                 break;
 146         case 0xe:
 147         case 0xf:
 148                 printk(BIOS_WARNING, "Invalid tck setting. "
 149                         "lower nibble is 0x%x\n", c & 0xf);
 150                 return CB_ERR;
 151         default:
 152                 low = (c & 0xf) * 10;
 153         }
 154
 155         *tck = ((high * 100 + low) << 8) / 100;
 156         return CB_SUCCESS;
 157 }
 158
 159 /**
 160  * \brief Decode SPD bcd style timings
 161  *
 162  * Decodes a raw SPD data from a DDR2 DIMM.
 163  * Returns cycle time in 1/256th ns.
 164  */
 165 static int spd_decode_bcd_time(u32 *bcd, u8 c)
 166 {
 167         u8 high, low;
 168
 169         high = c >> 4;
 170         low = c & 0xf;
 171         if (high >= 10 || low >= 10)
 172                 return CB_ERR;
 173
 174         *bcd = ((high * 10 + low) << 8) / 100;
 175         return CB_SUCCESS;
 176 }
 177
 178 /**
 179  * \brief Decode SPD tRP, tRRP cycle time
 180  *
 181  * Decodes a raw SPD data from a DDR2 DIMM.
 182  * Returns cycle time in 1/256th ns.
 183  */
 184 static u32 spd_decode_quarter_time(u8 c)
 185 {
 186         u8 high, low;
 187
 188         high = c >> 2;
 189         low = 25 * (c & 0x3);
 190
 191         return ((high * 100 + low) << 8) / 100;
 192 }
 193
 194 /**
 195  * \brief Decode SPD tRR time
 196  *
 197  * Decodes a raw SPD data from a DDR2 DIMM.
 198  * Returns cycle time in 1/256th us.
 199  */
 200 static int spd_decode_tRR_time(u32 *tRR, u8 c)
 201 {
 202         switch (c & ~0x80) {
 203         default:
 204                 printk(BIOS_WARNING, "Invalid tRR value 0x%x\n", c);
 205                 return CB_ERR;
 206         case 0x0:
 207                 *tRR = 15625 << 8;
 208                 break;
 209         case 0x1:
 210                 *tRR = 15625 << 6;
 211                 break;
 212         case 0x2:
 213                 *tRR = 15625 << 7;
 214                 break;
 215         case 0x3:
 216                 *tRR = 15625 << 9;
 217                 break;
 218         case 0x4:
 219                 *tRR = 15625 << 10;
 220                 break;
 221         case 0x5:
 222                 *tRR = 15625 << 11;
 223                 break;
 224         }
 225         return CB_SUCCESS;
 226 }
 227
 228 /**
 229  * \brief Decode SPD tRC,tRFC time
 230  *
 231  * Decodes a raw SPD data from a DDR2 DIMM.
 232  * Returns cycle time in 1/256th us.
 233  */
 234 static void spd_decode_tRCtRFC_time(u8 *spd_40_41_42, u32 *tRC, u32 *tRFC)
 235 {
 236         u8 b40, b41, b42;
 237
 238         b40 = spd_40_41_42[0];
 239         b41 = spd_40_41_42[1];
 240         b42 = spd_40_41_42[2];
 241
 242         *tRC = b41 * 100;
 243         *tRFC = b42 * 100;
 244
 245         if (b40 & 0x01)
 246                 *tRFC += 256 * 100;
 247
 248         switch ((b40 >> 1) & 0x07) {
 249         case 1:
 250                 *tRFC += 25;
 251                 break;
 252         case 2:
 253                 *tRFC += 33;
 254                 break;
 255         case 3:
 256                 *tRFC += 50;
 257                 break;
 258         case 4:
 259                 *tRFC += 66;
 260                 break;
 261         case 5:
 262                 *tRFC += 75;
 263                 break;
 264         default:
 265                 break;
 266         }
 267
 268         switch ((b40 >> 4) & 0x07) {
 269         case 1:
 270                 *tRC += 25;
 271                 break;
 272         case 2:
 273                 *tRC += 33;
 274                 break;
 275         case 3:
 276                 *tRC += 50;
 277                 break;
 278         case 4:
 279                 *tRC += 66;
 280                 break;
 281         case 5:
 282                 *tRC += 75;
 283                 break;
 284         default:
 285                 break;
 286         }
 287
 288         /* Convert to 1/256th us */
 289         *tRC = (*tRC << 8) / 100;
 290         *tRFC = (*tRFC << 8) / 100;
 291 }
 292
 293 /**
 294  * \brief Decode the raw SPD data
 295  *
 296  * Decodes a raw SPD data from a DDR2 DIMM, and organizes it into a
 297  * @ref dimm_attr structure. The SPD data must first be read in a contiguous
 298  * array, and passed to this function.
 299  *
 300  * @param dimm pointer to @ref dimm_attr structure where the decoded data is to
 301  *        be stored
 302  * @param spd array of raw data previously read from the SPD.
 303  *
 304  * @return @ref spd_status enumerator
 305  *         SPD_STATUS_OK -- decoding was successful
 306  *         SPD_STATUS_INVALID -- invalid SPD or not a DDR2 SPD
 307  *         SPD_STATUS_CRC_ERROR -- CRC did not verify
 308  *         SPD_STATUS_INVALID_FIELD -- A field with an invalid value was
 309  *             detected.
 310  */
 311 int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
 312 {
 313         u8 spd_size, cl, reg8;
 314         u16 eeprom_size;
 315         int ret = SPD_STATUS_OK;
 316
 317         memset(dimm, 0, sizeof(*dimm));
 318
 319         spd_size = spd_decode_spd_size_ddr2(spd[0]);
 320         eeprom_size = spd_decode_eeprom_size_ddr2(spd[1]);
 321
 322         printram("EEPROM with 0x%04x bytes\n", eeprom_size);
 323         printram("SPD contains 0x%02x bytes\n", spd_size);
 324
 325         if (spd_size < 64 || eeprom_size < 64) {
 326                 printk(BIOS_WARNING, "ERROR: SPD to small\n");
 327                 dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED;
 328                 return SPD_STATUS_INVALID;
 329         }
 330
 331         if (spd_ddr2_calc_checksum(spd, spd_size) != spd[63]) {
 332                 printk(BIOS_WARNING, "ERROR: SPD checksum error\n");
 333                 dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED;
 334                 return SPD_STATUS_CRC_ERROR;
 335         }
 336         dimm->checksum = spd[63];
 337
 338         reg8 = spd[62];
 339         if ((reg8 & 0xf0) != 0x10) {
 340                 printk(BIOS_WARNING,
 341                         "ERROR: Unsupported SPD revision %01x.%01x\n",
 342                         reg8 >> 4, reg8 & 0xf);
 343                 dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED;
 344                 return SPD_STATUS_INVALID;
 345         }
 346         dimm->rev = reg8;
 347         printram("  Revision           : %01x.%01x\n", dimm->rev >> 4, dimm->rev & 0xf);
 348
 349         reg8 = spd[2];
 350         printram("  Type               : 0x%02x\n", reg8);
 351         if (reg8 != 0x08) {
 352                 printk(BIOS_WARNING, "ERROR: Unsupported SPD type %x\n", reg8);
 353                 dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED;
 354                 return SPD_STATUS_INVALID;
 355         }
 356         dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR2;
 357
 358         dimm->row_bits = spd[3];
 359         printram("  Rows               : %u\n", dimm->row_bits);
 360         if ((dimm->row_bits > 31) ||
 361             ((dimm->row_bits > 15) && (dimm->rev < 0x13))) {
 362                 printk(BIOS_WARNING,
 363                         "SPD decode: invalid number of memory rows\n");
 364                 ret = SPD_STATUS_INVALID_FIELD;
 365         }
 366
 367         dimm->col_bits = spd[4];
 368         printram("  Columns            : %u\n", dimm->col_bits);
 369         if (dimm->col_bits > 15) {
 370                 printk(BIOS_WARNING,
 371                         "SPD decode: invalid number of memory columns\n");
 372                 ret = SPD_STATUS_INVALID_FIELD;
 373         }
 374
 375         dimm->ranks = (spd[5] & 0x7) + 1;
 376         printram("  Ranks              : %u\n", dimm->ranks);
 377
 378         dimm->mod_width = spd[6];
 379         printram("  Module data width  : x%u\n", dimm->mod_width);
 380         if (!dimm->mod_width) {
 381                 printk(BIOS_WARNING, "SPD decode: invalid module data width\n");
 382                 ret = SPD_STATUS_INVALID_FIELD;
 383         }
 384
 385         dimm->width = spd[13];
 386         printram("  SDRAM width        : x%u\n", dimm->width);
 387         if (!dimm->width) {
 388                 printk(BIOS_WARNING, "SPD decode: invalid SDRAM width\n");
 389                 ret = SPD_STATUS_INVALID_FIELD;
 390         }
 391
 392         dimm->banks = spd[17];
 393         printram("  Banks              : %u\n", dimm->banks);
 394         if (!dimm->banks) {
 395                 printk(BIOS_WARNING,
 396                         "SPD decode: invalid module banks count\n");
 397                 ret = SPD_STATUS_INVALID_FIELD;
 398         }
 399
 400         switch (spd[8]) {
 401         case 0:
 402                 dimm->flags.operable_5_00V = 1;
 403                 printram("  Voltage            : 5.0V\n");
 404                 break;
 405         case 1:
 406                 dimm->flags.operable_3_33V = 1;
 407                 printram("  Voltage            : 3.3V\n");
 408                 break;
 409         case 2:
 410                 dimm->flags.operable_1_50V = 1;
 411                 printram("  Voltage            : 1.5V\n");
 412                 break;
 413         case 3:
 414                 dimm->flags.operable_3_33V = 1;
 415                 printram("  Voltage            : 3.3V\n");
 416                 break;
 417         case 4:
 418                 dimm->flags.operable_2_50V = 1;
 419                 printram("  Voltage            : 2.5V\n");
 420                 break;
 421         case 5:
 422                 dimm->flags.operable_1_80V = 1;
 423                 printram("  Voltage            : 1.8V\n");
 424                 break;
 425         default:
 426                 printk(BIOS_WARNING, "SPD decode: unknown voltage level.\n");
 427                 ret = SPD_STATUS_INVALID_FIELD;
 428         }
 429
 430         dimm->cas_supported = spd[18];
 431         if ((dimm->cas_supported & 0x3) || !dimm->cas_supported) {
 432                 printk(BIOS_WARNING,
 433                         "SPD decode: invalid CAS support advertised.\n");
 434                 ret = SPD_STATUS_INVALID_FIELD;
 435         }
 436         printram("  Supported CAS mask : 0x%x\n", dimm->cas_supported);
 437
 438         if ((dimm->rev < 0x13) && (dimm->cas_supported & 0x80)) {
 439                 printk(BIOS_WARNING,
 440                         "SPD decode: invalid CAS support advertised.\n");
 441                 ret = SPD_STATUS_INVALID_FIELD;
 442         }
 443         if ((dimm->rev < 0x12) && (dimm->cas_supported & 0x40)) {
 444                 printk(BIOS_WARNING,
 445                         "SPD decode: invalid CAS support advertised.\n");
 446                 ret = SPD_STATUS_INVALID_FIELD;
 447         }
 448
 449         /* CL=X */
 450         cl = spd_get_msbs(dimm->cas_supported);
 451
 452         /* SDRAM Cycle time at Maximum Supported CAS Latency (CL), CL=X */
 453         if (spd_decode_tck_time(&dimm->cycle_time[cl], spd[9]) != CB_SUCCESS) {
 454                 printk(BIOS_WARNING,
 455                         "SPD decode: invalid min tCL for CAS%d\n", cl);
 456                 ret = SPD_STATUS_INVALID_FIELD;
 457         }
 458         /* SDRAM Access from Clock */
 459         if (spd_decode_bcd_time(&dimm->access_time[cl], spd[10])
 460                         != CB_SUCCESS) {
 461                 printk(BIOS_WARNING,
 462                         "SPD decode: invalid min tAC for CAS%d\n", cl);
 463                 ret = SPD_STATUS_INVALID_FIELD;
 464         }
 465
 466         if (dimm->cas_supported & (1 << (cl - 1))) {
 467                 /* Minimum Clock Cycle at CLX-1 */
 468                 if (spd_decode_tck_time(&dimm->cycle_time[cl - 1], spd[23])
 469                                 != CB_SUCCESS) {
 470                         printk(BIOS_WARNING,
 471                                 "SPD decode: invalid min tCL for CAS%d\n",
 472                                 cl - 1);
 473                         ret = SPD_STATUS_INVALID_FIELD;
 474                 }
 475                 /* Maximum Data Access Time (tAC) from Clock at CLX-1 */
 476                 if (spd_decode_bcd_time(&dimm->access_time[cl - 1], spd[24])
 477                                 != CB_SUCCESS) {
 478                         printk(BIOS_WARNING,
 479                                 "SPD decode: invalid min tAC for CAS%d\n",
 480                                 cl - 1);
 481                         ret = SPD_STATUS_INVALID_FIELD;
 482                 }
 483         }
 484         if (dimm->cas_supported & (1 << (cl - 2))) {
 485                 /* Minimum Clock Cycle at CLX-2 */
 486                 if (spd_decode_tck_time(&dimm->cycle_time[cl - 2], spd[25])
 487                                 != CB_SUCCESS) {
 488                         printk(BIOS_WARNING,
 489                                 "SPD decode: invalid min tCL for CAS%d\n",
 490                                 cl - 2);
 491                         ret = SPD_STATUS_INVALID_FIELD;
 492                 }
 493                 /* Maximum Data Access Time (tAC) from Clock at CLX-2 */
 494                 if (spd_decode_bcd_time(&dimm->access_time[cl - 2], spd[26])
 495                                 != CB_SUCCESS) {
 496                         printk(BIOS_WARNING,
 497                                 "SPD decode: invalid min tAC for CAS%d\n",
 498                                 cl - 2);
 499                         ret = SPD_STATUS_INVALID_FIELD;
 500                 }
 501         }
 502
 503         reg8 = (spd[31] >> 5) | (spd[31] << 3);
 504         if (!reg8) {
 505                 printk(BIOS_WARNING,
 506                         "SPD decode: invalid rank density.\n");
 507                 ret = SPD_STATUS_INVALID_FIELD;
 508         }
 509
 510         /* Rank density */
 511         dimm->ranksize_mb = 128 * reg8;
 512         /* Module density */
 513         dimm->size_mb = dimm->ranksize_mb * dimm->ranks;
 514         if (dimm->size_mb < 1024)
 515                 printram("  Capacity           : %u MB\n", dimm->size_mb);
 516         else
 517                 printram("  Capacity           : %u GB\n", dimm->size_mb >> 10);
 518
 519         /* SDRAM Maximum Cycle Time (tCKmax) */
 520         if (spd_decode_bcd_time(&dimm->tCK, spd[43]) != CB_SUCCESS) {
 521                 printk(BIOS_WARNING, "SPD decode: invalid Max tCK\n");
 522                 ret = SPD_STATUS_INVALID_FIELD;
 523         }
 524         /* Minimum Write Recovery Time (tWRmin) */
 525         dimm->tWR = spd_decode_quarter_time(spd[36]);
 526         /* Minimum RAS# to CAS# Delay Time (tRCDmin) */
 527         dimm->tRCD = spd_decode_quarter_time(spd[29]);
 528         /* Minimum Row Active to Row Active Delay Time (tRRDmin) */
 529         dimm->tRRD = spd_decode_quarter_time(spd[28]);
 530         /* Minimum Row Precharge Delay Time (tRPmin) */
 531         dimm->tRP = spd_decode_quarter_time(spd[27]);
 532         /* Minimum Active to Precharge Delay Time (tRASmin) */
 533         dimm->tRAS = spd[30] << 8;
 534         /* Minimum Active to Active/Refresh Delay Time (tRCmin) */
 535         /* Minimum Refresh Recovery Delay Time (tRFCmin) */
 536         spd_decode_tRCtRFC_time(&spd[40], &dimm->tRC, &dimm->tRFC);
 537         /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */
 538         dimm->tWTR = spd_decode_quarter_time(spd[37]);
 539         /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */
 540         dimm->tRTP = spd_decode_quarter_time(spd[38]);
 541         /* Data Input Setup Time Before Strobe */
 542         if (spd_decode_bcd_time(&dimm->tDS, spd[34]) != CB_SUCCESS) {
 543                 printk(BIOS_WARNING, "SPD decode: invalid tDS\n");
 544                 ret = SPD_STATUS_INVALID_FIELD;
 545         }
 546         /* Data Input Hold Time After Strobe */
 547         if (spd_decode_bcd_time(&dimm->tDH, spd[35]) != CB_SUCCESS) {
 548                 printk(BIOS_WARNING, "SPD decode: invalid tDH\n");
 549                 ret = SPD_STATUS_INVALID_FIELD;
 550         }
 551         /* SDRAM Device DQS-DQ Skew for DQS and associated DQ signals */
 552         dimm->tDQSQ = (spd[44] << 8) / 100;
 553         /* SDRAM Device Maximum Read Data Hold Skew Factor */
 554         dimm->tQHS = (spd[45] << 8) / 100;
 555         /* PLL Relock Time in us */
 556         dimm->tPLL = spd[46] << 8;
 557         /* Refresh rate in us */
 558         if (spd_decode_tRR_time(&dimm->tRR, spd[12]) != CB_SUCCESS)
 559                 ret = SPD_STATUS_INVALID_FIELD;
 560         dimm->flags.self_refresh = (spd[12] >> 7) & 1;
 561         printram("The assembly supports self refresh: %s\n",
 562                  dimm->flags.self_refresh ? "true" : "false");
 563
 564         /* Number of PLLs on DIMM */
 565         if (dimm->rev >= 0x11)
 566                 dimm->plls = (spd[21] >> 2) & 0x3;
 567
 568         /* SDRAM Thermal and Refresh Options */
 569         printram("  General features   :");
 570         if ((dimm->rev >= 0x12) && (spd[22] & 0x04)) {
 571                 dimm->flags.pasr = 1;
 572                 printram(" PASR");
 573         }
 574         if ((dimm->rev >= 0x12) && (spd[22] & 0x02)) {
 575                 dimm->flags.terminate_50ohms = 1;
 576                 printram(" 50Ohm");
 577         }
 578         if (spd[22] & 0x01) {
 579                 dimm->flags.weak_driver = 1;
 580                 printram(" WEAK_DRIVER");
 581         }
 582         printram("\n");
 583
 584         /* SDRAM Supported Burst length */
 585         printram("  Burst length       :");
 586         if (spd[16] & 0x08) {
 587                 dimm->flags.bl8 = 1;
 588                 printram(" BL8");
 589         }
 590         if (spd[16] & 0x04) {
 591                 dimm->flags.bl4 = 1;
 592                 printram(" BL4");
 593         }
 594         printram("\n");
 595
 596         dimm->dimm_type = spd[20] & SPD_DDR2_DIMM_TYPE_MASK;
 597         printram("  Dimm type          : %x\n", dimm->dimm_type);
 598
 599         dimm->flags.is_ecc = !!(spd[11] & 0x3);
 600         printram("  ECC support        : %x\n", dimm->flags.is_ecc);
 601
 602         dimm->flags.stacked = !!(spd[5] & 0x10);
 603         printram("  Package            : %s\n",
 604             dimm->flags.stacked ? "stack" : "planar");
 605
 606         if (spd_size > 71) {
 607                 memcpy(&dimm->manufacturer_id, &spd[64], 4);
 608                 printram("  Manufacturer ID    : %x\n", dimm->manufacturer_id);
 609         }
 610
 611         if (spd_size > 90) {
 612                 dimm->part_number[16] = 0;
 613                 memcpy(dimm->part_number, &spd[73], 16);
 614                 printram("  Part number        : %s\n", dimm->part_number);
 615         }
 616
 617         if (spd_size > 94) {
 618                 dimm->year = spd[93] + 2000;
 619                 dimm->weeks = spd[94];
 620                 printram("  Date               : %d week %d\n", dimm->year, dimm->weeks);
 621         }
 622
 623         if (spd_size > 98) {
 624                 memcpy(&dimm->serial, &spd[95], 4);
 625                 printram("  Serial number      : 0x%08x\n", dimm->serial);
 626         }
 627         return ret;
 628 }
 629
 630 /*
 631  * The information printed below has a more informational character, and is not
 632  * necessarily tied in to RAM init debugging. Hence, we stop using printram(),
 633  * and use the standard printk()'s below.
 634  */
 635
 636 static void print_ns(const char *msg, u32 val)
 637 {
 638         u32 mant, fp;
 639         mant = val / 256;
 640         fp = (val % 256) * 1000 / 256;
 641
 642         printk(BIOS_INFO, "%s%3u.%.3u ns\n", msg, mant, fp);
 643 }
 644
 645 static void print_us(const char *msg, u32 val)
 646 {
 647         u32 mant, fp;
 648         mant = val / 256;
 649         fp = (val % 256) * 1000 / 256;
 650
 651         printk(BIOS_INFO, "%s%3u.%.3u us\n", msg, mant, fp);
 652 }
 653
 654 /**
 655 * \brief Print the info in DIMM
 656 *
 657 * Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is
 658 * selected, or for a purely informative output.
 659 *
 660 * @param dimm pointer to already decoded @ref dimm_attr structure
 661 */
 662 void dram_print_spd_ddr2(const struct dimm_attr_ddr2_st *dimm)
 663 {
 664         char buf[32];
 665         int i;
 666
 667         printk(BIOS_INFO, "  Row    addr bits  : %u\n", dimm->row_bits);
 668         printk(BIOS_INFO, "  Column addr bits  : %u\n", dimm->col_bits);
 669         printk(BIOS_INFO, "  Number of ranks   : %u\n", dimm->ranks);
 670         printk(BIOS_INFO, "  DIMM Capacity     : %u MB\n", dimm->size_mb);
 671         printk(BIOS_INFO, "  Width             : x%u\n", dimm->width);
 672         printk(BIOS_INFO, "  Banks             : %u\n", dimm->banks);
 673
 674         /* CAS Latencies Supported */
 675         printk(BIOS_INFO, "  CAS latencies     :");
 676         for (i = 2; i < 8; i++) {
 677                 if (dimm->cas_supported & (1 << i))
 678                         printk(BIOS_INFO, " %u", i);
 679         }
 680         printk(BIOS_INFO, "\n");
 681
 682         for (i = 2; i < 8; i++) {
 683                 if (!(dimm->cas_supported & (1 << i)))
 684                         continue;
 685
 686                 strcpy(buf, "  tCK at CLx        : ");
 687                 /* Simple snprintf replacement */
 688                 buf[11] = '0' + i;
 689                 print_ns(buf, dimm->cycle_time[i]);
 690
 691                 strcpy(buf, "  tAC at CLx        : ");
 692                 /* Simple snprintf replacement */
 693                 buf[11] = '0' + i;
 694                 print_ns(buf, dimm->access_time[i]);
 695         }
 696         print_ns("  tCKmax            : ", dimm->tCK);
 697         print_ns("  tWRmin            : ", dimm->tWR);
 698         print_ns("  tRCDmin           : ", dimm->tRCD);
 699         print_ns("  tRRDmin           : ", dimm->tRRD);
 700         print_ns("  tRPmin            : ", dimm->tRP);
 701         print_ns("  tRASmin           : ", dimm->tRAS);
 702         print_ns("  tRCmin            : ", dimm->tRC);
 703         print_ns("  tRFCmin           : ", dimm->tRFC);
 704         print_ns("  tWTRmin           : ", dimm->tWTR);
 705         print_ns("  tRTPmin           : ", dimm->tRTP);
 706         print_ns("  tDS               : ", dimm->tDS);
 707         print_ns("  tDH               : ", dimm->tDH);
 708         print_ns("  tDQSQmax          : ", dimm->tDQSQ);
 709         print_ns("  tQHSmax           : ", dimm->tQHS);
 710         print_us("  tPLL              : ", dimm->tPLL);
 711         print_us("  tRR               : ", dimm->tRR);
 712 }
 713
 714 void normalize_tck(u32 *tclk)
 715 {
 716         if (*tclk <= TCK_800MHZ) {
 717                 *tclk = TCK_800MHZ;
 718         } else if (*tclk <= TCK_666MHZ) {
 719                 *tclk = TCK_666MHZ;
 720         } else if (*tclk <= TCK_533MHZ) {
 721                 *tclk = TCK_533MHZ;
 722         } else if (*tclk <= TCK_400MHZ) {
 723                 *tclk = TCK_400MHZ;
 724         } else if (*tclk <= TCK_333MHZ) {
 725                 *tclk = TCK_333MHZ;
 726         } else if (*tclk <= TCK_266MHZ) {
 727                 *tclk = TCK_266MHZ;
 728         } else if (*tclk <= TCK_200MHZ) {
 729                 *tclk = TCK_200MHZ;
 730         } else {
 731                 *tclk = 0;
 732                 printk(BIOS_ERR, "Too slow common tCLK found\n");
 733         }
 734 }