src/cpu/ti/am335x/pinmux.c

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3
   4 #include "pinmux.h"
   5
   6 #include <device/mmio.h>
   7
   8 static struct am335x_pinmux_regs *regs =
   9         (struct am335x_pinmux_regs *)(uintptr_t)AM335X_PINMUX_REG_ADDR;
  10
  11 void am335x_pinmux_uart0(void)
  12 {
  13         write32(&regs->uart0_rxd, MODE(0) | PULLUP_EN | RXACTIVE);
  14         write32(&regs->uart0_txd, MODE(0) | PULLUDEN);
  15 }
  16
  17 void am335x_pinmux_uart1(void)
  18 {
  19         write32(&regs->uart1_rxd, MODE(0) | PULLUP_EN | RXACTIVE);
  20         write32(&regs->uart1_txd, MODE(0) | PULLUDEN);
  21 }
  22
  23 void am335x_pinmux_uart2(void)
  24 {
  25         // UART2_RXD
  26         write32(&regs->spi0_sclk, MODE(1) | PULLUP_EN | RXACTIVE);
  27         // UART2_TXD
  28         write32(&regs->spi0_d0, MODE(1) | PULLUDEN);
  29 }
  30
  31 void am335x_pinmux_uart3(void)
  32 {
  33         // UART3_RXD
  34         write32(&regs->spi0_cs1, MODE(1) | PULLUP_EN | RXACTIVE);
  35         // UART3_TXD
  36         write32(&regs->ecap0_in_pwm0_out, MODE(1) | PULLUDEN);
  37 }
  38
  39 void am335x_pinmux_uart4(void)
  40 {
  41         // UART4_RXD
  42         write32(&regs->gpmc_wait0, MODE(6) | PULLUP_EN | RXACTIVE);
  43         // UART4_TXD
  44         write32(&regs->gpmc_wpn, MODE(6) | PULLUDEN);
  45 }
  46
  47 void am335x_pinmux_uart5(void)
  48 {
  49         // UART5_RXD
  50         write32(&regs->lcd_data9, MODE(4) | PULLUP_EN | RXACTIVE);
  51         // UART5_TXD
  52         write32(&regs->lcd_data8, MODE(4) | PULLUDEN);
  53 }
  54
  55 void am335x_pinmux_mmc0(int cd, int sk_evm)
  56 {
  57         write32(&regs->mmc0_dat0, MODE(0) | RXACTIVE | PULLUP_EN);
  58         write32(&regs->mmc0_dat1, MODE(0) | RXACTIVE | PULLUP_EN);
  59         write32(&regs->mmc0_dat2, MODE(0) | RXACTIVE | PULLUP_EN);
  60         write32(&regs->mmc0_dat3, MODE(0) | RXACTIVE | PULLUP_EN);
  61         write32(&regs->mmc0_clk, MODE(0) | RXACTIVE | PULLUP_EN);
  62         write32(&regs->mmc0_cmd, MODE(0) | RXACTIVE | PULLUP_EN);
  63         if (!sk_evm) {
  64                 // MMC0_WP
  65                 write32(&regs->mcasp0_aclkr, MODE(4) | RXACTIVE);
  66         }
  67         if (cd) {
  68                 // MMC0_CD
  69                 write32(&regs->spi0_cs1, MODE(5) | RXACTIVE | PULLUP_EN);
  70         }
  71 }
  72
  73 void am335x_pinmux_mmc1(void)
  74 {
  75         // MMC1_DAT0
  76         write32(&regs->gpmc_ad0, MODE(1) | RXACTIVE | PULLUP_EN);
  77         // MMC1_DAT1
  78         write32(&regs->gpmc_ad1, MODE(1) | RXACTIVE | PULLUP_EN);
  79         // MMC1_DAT2
  80         write32(&regs->gpmc_ad2, MODE(1) | RXACTIVE | PULLUP_EN);
  81         // MMC1_DAT3
  82         write32(&regs->gpmc_ad3, MODE(1) | RXACTIVE | PULLUP_EN);
  83         // MMC1_CLK
  84         write32(&regs->gpmc_csn1, MODE(2) | RXACTIVE | PULLUP_EN);
  85         // MMC1_CMD
  86         write32(&regs->gpmc_csn2, MODE(2) | RXACTIVE | PULLUP_EN);
  87         // MMC1_WP
  88         write32(&regs->gpmc_csn0, MODE(7) | RXACTIVE | PULLUP_EN);
  89         // MMC1_CD
  90         write32(&regs->gpmc_advn_ale, MODE(7) | RXACTIVE | PULLUP_EN);
  91 }
  92
  93 void am335x_pinmux_i2c0(void)
  94 {
  95         write32(&regs->i2c0_sda, MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL);
  96         write32(&regs->i2c0_scl, MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL);
  97 }
  98
  99 void am335x_pinmux_i2c1(void)
 100 {
 101         // I2C_DATA
 102         write32(&regs->spi0_d1, MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL);
 103         // I2C_SCLK
 104         write32(&regs->spi0_cs0, MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL);
 105 }
 106
 107 void am335x_pinmux_spi0(void)
 108 {
 109         write32(&regs->spi0_sclk, MODE(0) | RXACTIVE | PULLUDEN);
 110         write32(&regs->spi0_d0, MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN);
 111         write32(&regs->spi0_d1, MODE(0) | RXACTIVE | PULLUDEN);
 112         write32(&regs->spi0_cs0, MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN);
 113 }
 114
 115 void am335x_pinmux_gpio0_7(void)
 116 {
 117         write32(&regs->ecap0_in_pwm0_out, MODE(7) | PULLUDEN);
 118 }
 119
 120 void am335x_pinmux_rgmii1(void)
 121 {
 122         write32(&regs->mii1_txen, MODE(2));
 123         write32(&regs->mii1_rxdv, MODE(2) | RXACTIVE);
 124         write32(&regs->mii1_txd0, MODE(2));
 125         write32(&regs->mii1_txd1, MODE(2));
 126         write32(&regs->mii1_txd2, MODE(2));
 127         write32(&regs->mii1_txd3, MODE(2));
 128         write32(&regs->mii1_txclk, MODE(2));
 129         write32(&regs->mii1_rxclk, MODE(2) | RXACTIVE);
 130         write32(&regs->mii1_rxd0, MODE(2) | RXACTIVE);
 131         write32(&regs->mii1_rxd1, MODE(2) | RXACTIVE);
 132         write32(&regs->mii1_rxd2, MODE(2) | RXACTIVE);
 133         write32(&regs->mii1_rxd3, MODE(2) | RXACTIVE);
 134 }
 135
 136 void am335x_pinmux_mii1(void)
 137 {
 138         write32(&regs->mii1_rxerr, MODE(0) | RXACTIVE);
 139         write32(&regs->mii1_txen, MODE(0));
 140         write32(&regs->mii1_rxdv, MODE(0) | RXACTIVE);
 141         write32(&regs->mii1_txd0, MODE(0));
 142         write32(&regs->mii1_txd1, MODE(0));
 143         write32(&regs->mii1_txd2, MODE(0));
 144         write32(&regs->mii1_txd3, MODE(0));
 145         write32(&regs->mii1_txclk, MODE(0) | RXACTIVE);
 146         write32(&regs->mii1_rxclk, MODE(0) | RXACTIVE);
 147         write32(&regs->mii1_rxd0, MODE(0) | RXACTIVE);
 148         write32(&regs->mii1_rxd1, MODE(0) | RXACTIVE);
 149         write32(&regs->mii1_rxd2, MODE(0) | RXACTIVE);
 150         write32(&regs->mii1_rxd3, MODE(0) | RXACTIVE);
 151         write32(&regs->mdio_data, MODE(0) | RXACTIVE | PULLUP_EN);
 152         write32(&regs->mdio_clk, MODE(0) | PULLUP_EN);
 153 }
 154
 155 void am335x_pinmux_nand(void)
 156 {
 157         write32(&regs->gpmc_ad0, MODE(0) | PULLUP_EN | RXACTIVE);
 158         write32(&regs->gpmc_ad1, MODE(0) | PULLUP_EN | RXACTIVE);
 159         write32(&regs->gpmc_ad2, MODE(0) | PULLUP_EN | RXACTIVE);
 160         write32(&regs->gpmc_ad3, MODE(0) | PULLUP_EN | RXACTIVE);
 161         write32(&regs->gpmc_ad4, MODE(0) | PULLUP_EN | RXACTIVE);
 162         write32(&regs->gpmc_ad5, MODE(0) | PULLUP_EN | RXACTIVE);
 163         write32(&regs->gpmc_ad6, MODE(0) | PULLUP_EN | RXACTIVE);
 164         write32(&regs->gpmc_ad7, MODE(0) | PULLUP_EN | RXACTIVE);
 165         write32(&regs->gpmc_wait0, MODE(0) | RXACTIVE | PULLUP_EN);
 166         write32(&regs->gpmc_wpn, MODE(7) | PULLUP_EN | RXACTIVE);
 167         write32(&regs->gpmc_csn0, MODE(0) | PULLUDEN);
 168         write32(&regs->gpmc_advn_ale, MODE(0) | PULLUDEN);
 169         write32(&regs->gpmc_oen_ren, MODE(0) | PULLUDEN);
 170         write32(&regs->gpmc_wen, MODE(0) | PULLUDEN);
 171         write32(&regs->gpmc_be0n_cle, MODE(0) | PULLUDEN);
 172 }