src/commonlib/include/commonlib/sd_mmc_ctrlr.h

   1 /* This file is part of the coreboot project. */
   2 /* SPDX-License-Identifier: GPL-2.0-or-later */
   3 /*
   4  * Controller independent definitions
   5  */
   6 #ifndef __COMMONLIB_SD_MMC_CTRLR_H__
   7 #define __COMMONLIB_SD_MMC_CTRLR_H__
   8
   9 #include <stdint.h>
  10
  11 /* Error values returned by the storage drivers */
  12 #define CARD_UNUSABLE_ERR       -17 /* Unusable Card */
  13 #define CARD_COMM_ERR           -18 /* Communications Error */
  14 #define CARD_TIMEOUT            -19
  15 #define CARD_IN_PROGRESS        -20 /* operation is in progress */
  16
  17 struct mmc_command {
  18         uint16_t cmdidx;
  19
  20 /* Common commands */
  21 #define MMC_CMD_GO_IDLE_STATE           0
  22 #define MMC_CMD_SEND_OP_COND            1
  23 #define MMC_CMD_ALL_SEND_CID            2
  24 #define MMC_CMD_SET_DSR                 4
  25 #define MMC_CMD_SELECT_CARD             7
  26 #define MMC_CMD_SEND_CSD                9
  27 #define MMC_CMD_SEND_CID                10
  28 #define MMC_CMD_STOP_TRANSMISSION       12
  29 #define MMC_CMD_SEND_STATUS             13
  30 #define MMC_CMD_SET_BLOCKLEN            16
  31 #define MMC_CMD_READ_SINGLE_BLOCK       17
  32 #define MMC_CMD_READ_MULTIPLE_BLOCK     18
  33 #define MMC_CMD_WRITE_SINGLE_BLOCK      24
  34 #define MMC_CMD_WRITE_MULTIPLE_BLOCK    25
  35 #define MMC_CMD_APP_CMD                 55
  36
  37 /* MMC specific commands */
  38 #define MMC_CMD_SET_RELATIVE_ADDR       3
  39 #define MMC_CMD_SWITCH                  6
  40 #define MMC_CMD_SEND_EXT_CSD            8
  41 #define MMC_CMD_AUTO_TUNING_SEQUENCE    21
  42 #define MMC_CMD_ERASE_GROUP_START       35
  43 #define MMC_CMD_ERASE_GROUP_END         36
  44 #define MMC_CMD_ERASE                   38
  45 #define MMC_CMD_SPI_READ_OCR            58
  46 #define MMC_CMD_SPI_CRC_ON_OFF          59
  47
  48 /* SD specific commands */
  49 #define SD_CMD_SEND_RELATIVE_ADDR       3
  50 #define SD_CMD_SWITCH_FUNC              6
  51 #define SD_CMD_SEND_IF_COND             8
  52 #define SD_CMD_ERASE_WR_BLK_START       32
  53 #define SD_CMD_ERASE_WR_BLK_END         33
  54
  55 /* SD specific APP commands */
  56 #define SD_CMD_APP_SET_BUS_WIDTH        6
  57 #define SD_CMD_APP_SEND_OP_COND         41
  58 #define SD_CMD_APP_SEND_SCR             51
  59
  60         uint32_t resp_type;
  61
  62 #define CARD_RSP_PRESENT (1 << 0)
  63 #define CARD_RSP_136    (1 << 1)                /* 136 bit response */
  64 #define CARD_RSP_CRC    (1 << 2)                /* expect valid crc */
  65 #define CARD_RSP_BUSY   (1 << 3)                /* card may send busy */
  66 #define CARD_RSP_OPCODE (1 << 4)                /* response contains opcode */
  67
  68 #define CARD_RSP_NONE   (0)
  69 #define CARD_RSP_R1     (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE)
  70 #define CARD_RSP_R1b    (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE| \
  71                         CARD_RSP_BUSY)
  72 #define CARD_RSP_R2     (CARD_RSP_PRESENT|CARD_RSP_136|CARD_RSP_CRC)
  73 #define CARD_RSP_R3     (CARD_RSP_PRESENT)
  74 #define CARD_RSP_R4     (CARD_RSP_PRESENT)
  75 #define CARD_RSP_R5     (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE)
  76 #define CARD_RSP_R6     (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE)
  77 #define CARD_RSP_R7     (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE)
  78
  79         uint32_t cmdarg;
  80
  81 #define MMC_TRIM_ARG                    0x1
  82 #define MMC_SECURE_ERASE_ARG            0x80000000
  83
  84         uint32_t response[4];
  85         uint32_t flags;
  86
  87 #define CMD_FLAG_IGNORE_INHIBIT 1
  88 };
  89
  90 #define SD_SWITCH_CHECK         0
  91 #define SD_SWITCH_SWITCH        1
  92
  93 #define SD_DATA_4BIT            0x00040000
  94
  95 /* SCR definitions in different words */
  96 #define SD_HIGHSPEED_BUSY       0x00020000
  97 #define SD_HIGHSPEED_SUPPORTED  0x00020000
  98
  99 struct mmc_data {
 100         union {
 101                 char *dest;
 102                 const char *src;
 103         };
 104         uint32_t flags;
 105
 106 #define DATA_FLAG_READ          1
 107 #define DATA_FLAG_WRITE         2
 108
 109         uint32_t blocks;
 110         uint32_t blocksize;
 111 };
 112
 113 struct sd_mmc_ctrlr {
 114         int (*send_cmd)(struct sd_mmc_ctrlr *ctrlr,
 115                 struct mmc_command *cmd, struct mmc_data *data);
 116         void (*set_ios)(struct sd_mmc_ctrlr *ctrlr);
 117         void (*tuning_start)(struct sd_mmc_ctrlr *ctrlr, int retune);
 118         int (*is_tuning_complete)(struct sd_mmc_ctrlr *ctrlr, int *successful);
 119
 120         int initialized;
 121         unsigned int version;
 122         uint32_t voltages;
 123
 124 #define MMC_VDD_165_195         0x00000080      /* VDD voltage 1.65 - 1.95 */
 125 #define MMC_VDD_20_21           0x00000100      /* VDD voltage 2.0 ~ 2.1 */
 126 #define MMC_VDD_21_22           0x00000200      /* VDD voltage 2.1 ~ 2.2 */
 127 #define MMC_VDD_22_23           0x00000400      /* VDD voltage 2.2 ~ 2.3 */
 128 #define MMC_VDD_23_24           0x00000800      /* VDD voltage 2.3 ~ 2.4 */
 129 #define MMC_VDD_24_25           0x00001000      /* VDD voltage 2.4 ~ 2.5 */
 130 #define MMC_VDD_25_26           0x00002000      /* VDD voltage 2.5 ~ 2.6 */
 131 #define MMC_VDD_26_27           0x00004000      /* VDD voltage 2.6 ~ 2.7 */
 132 #define MMC_VDD_27_28           0x00008000      /* VDD voltage 2.7 ~ 2.8 */
 133 #define MMC_VDD_28_29           0x00010000      /* VDD voltage 2.8 ~ 2.9 */
 134 #define MMC_VDD_29_30           0x00020000      /* VDD voltage 2.9 ~ 3.0 */
 135 #define MMC_VDD_30_31           0x00040000      /* VDD voltage 3.0 ~ 3.1 */
 136 #define MMC_VDD_31_32           0x00080000      /* VDD voltage 3.1 ~ 3.2 */
 137 #define MMC_VDD_32_33           0x00100000      /* VDD voltage 3.2 ~ 3.3 */
 138 #define MMC_VDD_33_34           0x00200000      /* VDD voltage 3.3 ~ 3.4 */
 139 #define MMC_VDD_34_35           0x00400000      /* VDD voltage 3.4 ~ 3.5 */
 140 #define MMC_VDD_35_36           0x00800000      /* VDD voltage 3.5 ~ 3.6 */
 141
 142 #define MMC_VDD_165_195_SHIFT   7
 143
 144         uint32_t clock_base;    /* Controller's base clock */
 145         uint32_t f_min;
 146         uint32_t f_max;
 147         uint32_t request_hz;    /* Desired clock frequency */
 148         uint32_t bus_hz;        /* Actual bus clock frequency */
 149
 150 #define CLOCK_KHZ               1000
 151 #define CLOCK_MHZ               (1000 * CLOCK_KHZ)
 152 #define CLOCK_20MHZ             (20 * CLOCK_MHZ)
 153 #define CLOCK_25MHZ             (25 * CLOCK_MHZ)
 154 #define CLOCK_26MHZ             (26 * CLOCK_MHZ)
 155 #define CLOCK_50MHZ             (50 * CLOCK_MHZ)
 156 #define CLOCK_52MHZ             (52 * CLOCK_MHZ)
 157 #define CLOCK_200MHZ            (200 * CLOCK_MHZ)
 158
 159         uint32_t bus_width;
 160         uint32_t caps;
 161
 162 /* Generic controller & driver capabilities.  Controller specific capabilities
 163  * start at 0x00010000
 164  */
 165 #define DRVR_CAP_4BIT                           0x00000001
 166 #define DRVR_CAP_8BIT                           0x00000002
 167 #define DRVR_CAP_AUTO_CMD12                     0x00000004
 168 #define DRVR_CAP_HC                             0x00000008
 169 #define DRVR_CAP_HS                             0x00000010
 170 #define DRVR_CAP_HS52                           0x00000020
 171 #define DRVR_CAP_HS200                          0x00000040
 172 #define DRVR_CAP_HS400                          0x00000080
 173 #define DRVR_CAP_ENHANCED_STROBE                0x00000100
 174 #define DRVR_CAP_REMOVABLE                      0x00000200
 175 #define DRVR_CAP_DMA_64BIT                      0x00000400
 176 #define DRVR_CAP_HS200_TUNING                   0x00000800
 177
 178         uint32_t b_max;
 179         uint32_t timing;
 180
 181 #define BUS_TIMING_LEGACY       0
 182 #define BUS_TIMING_MMC_HS       1
 183 #define BUS_TIMING_SD_HS        2
 184 #define BUS_TIMING_UHS_SDR12    3
 185 #define BUS_TIMING_UHS_SDR25    4
 186 #define BUS_TIMING_UHS_SDR50    5
 187 #define BUS_TIMING_UHS_SDR104   6
 188 #define BUS_TIMING_UHS_DDR50    7
 189 #define BUS_TIMING_MMC_DDR52    8
 190 #define BUS_TIMING_MMC_HS200    9
 191 #define BUS_TIMING_MMC_HS400    10
 192 #define BUS_TIMING_MMC_HS400ES  11
 193
 194         uint32_t mdelay_before_cmd0;
 195         uint32_t mdelay_after_cmd0;
 196         uint32_t udelay_wait_after_cmd;
 197 };
 198
 199 /* SOC specific routine to override ctrlr->caps and .voltages
 200  *
 201  * Set/clear the necessary DRVR_CAP_xxx bits in ctrlr->caps to specify the
 202  * controllers capabilities and driver workarounds.
 203  *
 204  * Set/clear the necessary MMC_VDD_xxx bits in ctrlr->voltages to specify the
 205  * controllers power support.
 206  */
 207 void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr *ctrlr);
 208
 209 /* Optional routines to support logging */
 210 void sdhc_log_command(struct mmc_command *cmd);
 211 void sdhc_log_command_issued(void);
 212 void sdhc_log_response(uint32_t entries, uint32_t *response);
 213 void sdhc_log_ret(int ret);
 214
 215 #endif /* __COMMONLIB_SD_MMC_CTRLR_H__ */