src/mainboard/51nb/x210/devicetree.cb

   1 chip soc/intel/skylake
   2
   3         # Enable Panel as eDP and configure power delays
   4         register "gpu_pp_up_delay_ms"             = "210"       # T3
   5         register "gpu_pp_down_delay_ms"           = "500"       # T10
   6         register "gpu_pp_cycle_delay_ms"          = "5000"      # T12
   7         register "gpu_pp_backlight_on_delay_ms"   = "1"         # T7
   8         register "gpu_pp_backlight_off_delay_ms"  = "200"       # T9
   9
  10         # Enable deep Sx states
  11         register "deep_s3_enable_ac" = "1"
  12         register "deep_s3_enable_dc" = "1"
  13         register "deep_s5_enable_ac" = "1"
  14         register "deep_s5_enable_dc" = "1"
  15         register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
  16
  17         register "eist_enable" = "1"
  18
  19         # GPE configuration
  20         # Note that GPE events called out in ASL code rely on this
  21         # route. i.e. If this route changes then the affected GPE
  22         # offset bits also need to be changed.
  23         register "gpe0_dw0" = "GPP_C"
  24         register "gpe0_dw1" = "GPP_D"
  25         register "gpe0_dw2" = "GPP_E"
  26
  27         register "gen1_dec" = "0x000c0081"
  28         register "gen2_dec" = "0x000c0681"
  29         register "gen3_dec" = "0x000c1641"
  30
  31         # Disable DPTF
  32         register "dptf_enable" = "0"
  33
  34         # FSP Configuration
  35         register "SataSalpSupport" = "1"
  36         register "SataMode" = "0"
  37
  38         # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2
  39         register "SataPortsEnable[0]" = "1"
  40         register "SataPortsEnable[1]" = "1"
  41         register "SataPortsEnable[2]" = "1"
  42         register "SataPortsDevSlp[0]" = "1"
  43         register "SataPortsDevSlp[1]" = "1"
  44         register "SataPortsDevSlp[2]" = "1"
  45         register "DspEnable" = "0"
  46         register "IoBufferOwnership" = "0"
  47         register "SsicPortEnable" = "0"
  48         register "ScsEmmcHs400Enabled" = "0"
  49         register "SkipExtGfxScan" = "1"
  50         register "HeciEnabled" = "1"
  51         register "SaGv" = "SaGv_Enabled"
  52         register "PmConfigSlpS3MinAssert" = "2"         # 50ms
  53         register "PmConfigSlpS4MinAssert" = "1"         # 1s
  54         register "PmConfigSlpSusMinAssert" = "3"        # 500ms
  55         register "PmConfigSlpAMinAssert" = "3"          # 2s
  56
  57         register "serirq_mode" = "SERIRQ_CONTINUOUS"
  58
  59         # Enable Root Ports 3, 4 and 9
  60         register "PcieRpEnable[2]" = "1" # Ethernet controller
  61         register "PcieRpClkReqSupport[2]" = "1"
  62         register "PcieRpClkReqNumber[2]" = "0"
  63         register "PcieRpClkSrcNumber[2]" = "0"
  64         register "PcieRpAdvancedErrorReporting[2]" = "1"
  65         register "PcieRpLtrEnable[2]" = "1"
  66
  67         register "PcieRpEnable[3]" = "1" # Wireless controller
  68         register "PcieRpClkReqSupport[3]" = "1"
  69         register "PcieRpClkReqNumber[3]" = "1"
  70         register "PcieRpClkSrcNumber[3]" = "1"
  71         register "PcieRpAdvancedErrorReporting[3]" = "1"
  72         register "PcieRpLtrEnable[3]" = "1"
  73
  74         register "PcieRpEnable[8]" = "1" # NVMe controller
  75         register "PcieRpClkReqSupport[8]" = "1"
  76         register "PcieRpClkReqNumber[8]" = "4"
  77         register "PcieRpClkSrcNumber[8]" = "4"
  78         register "PcieRpAdvancedErrorReporting[8]" = "1"
  79         register "PcieRpLtrEnable[8]" = "1"
  80
  81         register "usb2_ports[0]" = "USB2_PORT_MID(OC1)"         # Type-A Port (left)
  82         register "usb2_ports[1]" = "USB2_PORT_MID(OC1)"         # Type-A Port (left)
  83         register "usb2_ports[2]" = "USB2_PORT_FLEX(OC_SKIP)"    # FPR
  84         register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)"    # SD
  85         register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)"    # INT
  86         register "usb2_ports[5]" = "USB2_PORT_MID(OC1)"         # Type-A Port (right)
  87         register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"    # Webcam
  88         register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"     # mPCIe / WiFi Port
  89         register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"     # mSATA / WWAN Port
  90
  91         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"     # Type-A Port (left)
  92         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"     # Type-A Port (left)
  93
  94         # PL1 override 25W
  95         # PL2 override 44W
  96         register "power_limits_config" = "{
  97                 .tdp_pl1_override = 25,
  98                 .tdp_pl2_override = 44,
  99         }"
 100
 101         # Send an extra VR mailbox command for the PS4 exit issue
 102         register "SendVrMbxCmd" = "2"
 103
 104         # Lock Down
 105         register "common_soc_config" = "{
 106                 .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 107         }"
 108
 109         device cpu_cluster 0 on
 110                 device lapic 0 on end
 111         end
 112         device domain 0 on
 113                 device pci 00.0 on  end # Host Bridge
 114                 device pci 02.0 on  end # Integrated Graphics Device
 115                 device pci 04.0 on  end # SA thermal subsystem
 116                 device pci 14.0 on  end # USB xHCI
 117                 device pci 14.1 off end # USB xDCI (OTG)
 118                 device pci 14.2 on  end # Thermal Subsystem
 119                 device pci 14.3 off end # Camera
 120                 device pci 16.0 on  end # Management Engine Interface 1
 121                 device pci 16.1 off end # Management Engine Interface 2
 122                 device pci 16.2 off end # Management Engine IDE-R
 123                 device pci 16.3 off end # Management Engine KT Redirection
 124                 device pci 16.4 off end # Management Engine Interface 3
 125                 device pci 17.0 on  end # SATA
 126                 device pci 1c.0 off end # PCI Express Port 1
 127                 device pci 1c.1 off end # PCI Express Port 2
 128                 device pci 1c.2 on  end # PCI Express Port 3
 129                 device pci 1c.3 on  end # PCI Express Port 4
 130                 device pci 1c.4 off end # PCI Express Port 5
 131                 device pci 1c.5 off end # PCI Express Port 6
 132                 device pci 1c.6 off end # PCI Express Port 7
 133                 device pci 1c.7 off end # PCI Express Port 8
 134                 device pci 1d.0 on  end # PCI Express Port 9
 135                 device pci 1d.1 off end # PCI Express Port 10
 136                 device pci 1d.2 off end # PCI Express Port 11
 137                 device pci 1d.3 off end # PCI Express Port 12
 138                 device pci 1e.6 off end # SDXC
 139                 device pci 1f.0 on
 140                         chip ec/51nb/npce985la0dx
 141                                 device pnp 0c09.0 on end
 142                                 device pnp 4e.5   on end
 143                                 device pnp 4e.6   on end
 144                                 device pnp 4e.11  on end
 145                         end
 146                 end # LPC Interface
 147                 device pci 1f.1 off end # P2SB
 148                 device pci 1f.2 on  end # Power Management Controller
 149                 device pci 1f.3 on  end # Intel HDA
 150                 device pci 1f.4 on  end # SMBus
 151                 device pci 1f.5 off end # PCH SPI
 152                 device pci 1f.6 off end # GbE
 153         end
 154 end