2 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
3 2005.12 yhlu add CONFIG_RAMBASE above 1M support for SMP
4 2008.05 stepan add support for going back to sipi wait state
7 #include <cpu/x86/lapic.h>
10 #include <console/console.h>
12 #include <device/device.h>
13 #include <device/path.h>
14 #include <smp/atomic.h>
15 #include <smp/spinlock.h>
19 /* This is a lot more paranoid now, since Linux can NOT handle
20 * being told there is a CPU when none exists. So any errors
21 * will return 0, meaning no CPU.
23 * We actually handling that case by noting which cpus startup
24 * and not telling anyone about the ones that dont.
26 static unsigned long get_valid_start_eip(unsigned long orig_start_eip
)
28 return (unsigned long)orig_start_eip
& 0xffff; // 16 bit to avoid 0xa0000
31 #if CONFIG_HAVE_ACPI_RESUME == 1
33 char *lowmem_backup_ptr
;
34 int lowmem_backup_size
;
37 extern char _secondary_start
[];
39 static void copy_secondary_start_to_1m_below(void)
41 extern char _secondary_start_end
[];
42 unsigned long code_size
;
43 unsigned long start_eip
;
45 /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S
46 Also We need to copy the _secondary_start to the below 1M region
48 start_eip
= get_valid_start_eip((unsigned long)_secondary_start
);
49 code_size
= (unsigned long)_secondary_start_end
- (unsigned long)_secondary_start
;
51 #if CONFIG_HAVE_ACPI_RESUME == 1
52 /* need to save it for RAM resume */
53 lowmem_backup_size
= code_size
;
54 lowmem_backup
= malloc(code_size
);
55 lowmem_backup_ptr
= (char *)start_eip
;
57 if (lowmem_backup
== NULL
)
58 die("Out of backup memory\n");
60 memcpy(lowmem_backup
, lowmem_backup_ptr
, lowmem_backup_size
);
62 /* copy the _secondary_start to the ram below 1M*/
63 memcpy((unsigned char *)start_eip
, (unsigned char *)_secondary_start
, code_size
);
65 printk(BIOS_DEBUG
, "start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip
, ((unsigned long)_secondary_start
- start_eip
), code_size
);
68 static int lapic_start_cpu(unsigned long apicid
)
71 unsigned long send_status
, accept_status
, start_eip
;
72 int j
, num_starts
, maxlvt
;
75 * Starting actual IPI sequence...
78 printk(BIOS_SPEW
, "Asserting INIT.\n");
81 * Turn INIT on target chip
83 lapic_write_around(LAPIC_ICR2
, SET_LAPIC_DEST_FIELD(apicid
));
89 lapic_write_around(LAPIC_ICR
, LAPIC_INT_LEVELTRIG
| LAPIC_INT_ASSERT
92 printk(BIOS_SPEW
, "Waiting for send to finish...\n");
95 printk(BIOS_SPEW
, "+");
97 send_status
= lapic_read(LAPIC_ICR
) & LAPIC_ICR_BUSY
;
98 } while (send_status
&& (timeout
++ < 1000));
99 if (timeout
>= 1000) {
100 printk(BIOS_ERR
, "CPU %ld: First apic write timed out. Disabling\n",
103 printk(BIOS_ERR
, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR
));
104 if (lapic_read(LAPIC_ESR
)) {
105 printk(BIOS_ERR
, "Try to reset ESR\n");
106 lapic_write_around(LAPIC_ESR
, 0);
107 printk(BIOS_ERR
, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR
));
111 #if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
115 printk(BIOS_SPEW
, "Deasserting INIT.\n");
118 lapic_write_around(LAPIC_ICR2
, SET_LAPIC_DEST_FIELD(apicid
));
121 lapic_write_around(LAPIC_ICR
, LAPIC_INT_LEVELTRIG
| LAPIC_DM_INIT
);
123 printk(BIOS_SPEW
, "Waiting for send to finish...\n");
126 printk(BIOS_SPEW
, "+");
128 send_status
= lapic_read(LAPIC_ICR
) & LAPIC_ICR_BUSY
;
129 } while (send_status
&& (timeout
++ < 1000));
130 if (timeout
>= 1000) {
131 printk(BIOS_ERR
, "CPU %ld: Second apic write timed out. Disabling\n",
137 start_eip
= get_valid_start_eip((unsigned long)_secondary_start
);
139 #if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
146 * Run STARTUP IPI loop.
148 printk(BIOS_SPEW
, "#startup loops: %d.\n", num_starts
);
152 for (j
= 1; j
<= num_starts
; j
++) {
153 printk(BIOS_SPEW
, "Sending STARTUP #%d to %lu.\n", j
, apicid
);
154 lapic_read_around(LAPIC_SPIV
);
155 lapic_write(LAPIC_ESR
, 0);
156 lapic_read(LAPIC_ESR
);
157 printk(BIOS_SPEW
, "After apic_write.\n");
164 lapic_write_around(LAPIC_ICR2
, SET_LAPIC_DEST_FIELD(apicid
));
166 /* Boot on the stack */
167 /* Kick the second */
168 lapic_write_around(LAPIC_ICR
, LAPIC_DM_STARTUP
169 | (start_eip
>> 12));
172 * Give the other CPU some time to accept the IPI.
176 printk(BIOS_SPEW
, "Startup point 1.\n");
178 printk(BIOS_SPEW
, "Waiting for send to finish...\n");
181 printk(BIOS_SPEW
, "+");
183 send_status
= lapic_read(LAPIC_ICR
) & LAPIC_ICR_BUSY
;
184 } while (send_status
&& (timeout
++ < 1000));
187 * Give the other CPU some time to accept the IPI.
191 * Due to the Pentium erratum 3AP.
194 lapic_read_around(LAPIC_SPIV
);
195 lapic_write(LAPIC_ESR
, 0);
197 accept_status
= (lapic_read(LAPIC_ESR
) & 0xEF);
198 if (send_status
|| accept_status
)
201 printk(BIOS_SPEW
, "After Startup.\n");
203 printk(BIOS_WARNING
, "APIC never delivered???\n");
205 printk(BIOS_WARNING
, "APIC delivery error (%lx).\n", accept_status
);
206 if (send_status
|| accept_status
)
211 /* Number of cpus that are currently running in coreboot */
212 static atomic_t active_cpus
= ATOMIC_INIT(1);
214 /* start_cpu_lock covers last_cpu_index and secondary_stack.
215 * Only starting one cpu at a time let's me remove the logic
216 * for select the stack from assembly language.
218 * In addition communicating by variables to the cpu I
219 * am starting allows me to veryify it has started before
223 static spinlock_t start_cpu_lock
= SPIN_LOCK_UNLOCKED
;
224 static unsigned last_cpu_index
= 0;
225 volatile unsigned long secondary_stack
;
227 int start_cpu(device_t cpu
)
229 extern unsigned char _estack
[];
230 struct cpu_info
*info
;
231 unsigned long stack_end
;
232 unsigned long apicid
;
237 spin_lock(&start_cpu_lock
);
239 /* Get the cpu's apicid */
240 apicid
= cpu
->path
.apic
.apic_id
;
242 /* Get an index for the new processor */
243 index
= ++last_cpu_index
;
245 /* Find end of the new processors stack */
246 stack_end
= ((unsigned long)_estack
) - (CONFIG_STACK_SIZE
*index
) - sizeof(struct cpu_info
);
248 /* Record the index and which cpu structure we are using */
249 info
= (struct cpu_info
*)stack_end
;
253 /* Advertise the new stack to start_cpu */
254 secondary_stack
= stack_end
;
256 /* Until the cpu starts up report the cpu is not enabled */
258 cpu
->initialized
= 0;
261 result
= lapic_start_cpu(apicid
);
265 /* Wait 1s or until the new the new cpu calls in */
266 for(count
= 0; count
< 100000 ; count
++) {
267 if (secondary_stack
== 0) {
275 spin_unlock(&start_cpu_lock
);
279 #if CONFIG_AP_IN_SIPI_WAIT == 1
281 * Normally this function is defined in lapic.h as an always inline function
282 * that just keeps the CPU in a hlt() loop. This does not work on all CPUs.
283 * I think all hyperthreading CPUs might need this version, but I could only
284 * verify this on the Intel Core Duo
286 void stop_this_cpu(void)
289 unsigned long send_status
;
292 id
= lapic_read(LAPIC_ID
) >> 24;
294 printk(BIOS_DEBUG
, "CPU %ld going down...\n", id
);
296 /* send an LAPIC INIT to myself */
297 lapic_write_around(LAPIC_ICR2
, SET_LAPIC_DEST_FIELD(id
));
298 lapic_write_around(LAPIC_ICR
, LAPIC_INT_LEVELTRIG
| LAPIC_INT_ASSERT
| LAPIC_DM_INIT
);
300 /* wait for the ipi send to finish */
302 // When these two printk(BIOS_SPEW, ...) calls are not removed, the
303 // machine will hang when log level is SPEW. Why?
304 printk(BIOS_SPEW
, "Waiting for send to finish...\n");
309 printk(BIOS_SPEW
, "+");
312 send_status
= lapic_read(LAPIC_ICR
) & LAPIC_ICR_BUSY
;
313 } while (send_status
&& (timeout
++ < 1000));
314 if (timeout
>= 1000) {
315 printk(BIOS_ERR
, "timed out\n");
319 printk(BIOS_SPEW
, "Deasserting INIT.\n");
320 /* Deassert the LAPIC INIT */
321 lapic_write_around(LAPIC_ICR2
, SET_LAPIC_DEST_FIELD(id
));
322 lapic_write_around(LAPIC_ICR
, LAPIC_INT_LEVELTRIG
| LAPIC_DM_INIT
);
324 printk(BIOS_SPEW
, "Waiting for send to finish...\n");
327 printk(BIOS_SPEW
, "+");
329 send_status
= lapic_read(LAPIC_ICR
) & LAPIC_ICR_BUSY
;
330 } while (send_status
&& (timeout
++ < 1000));
331 if (timeout
>= 1000) {
332 printk(BIOS_ERR
, "timed out\n");
341 /* C entry point of secondary cpus */
342 void secondary_cpu_init(void)
344 atomic_inc(&active_cpus
);
345 #if CONFIG_SERIAL_CPU_INIT == 1
346 #if CONFIG_MAX_CPUS>2
347 spin_lock(&start_cpu_lock
);
351 #if CONFIG_SERIAL_CPU_INIT == 1
352 #if CONFIG_MAX_CPUS>2
353 spin_unlock(&start_cpu_lock
);
357 atomic_dec(&active_cpus
);
362 static void start_other_cpus(struct bus
*cpu_bus
, device_t bsp_cpu
)
365 /* Loop through the cpus once getting them started */
367 for(cpu
= cpu_bus
->children
; cpu
; cpu
= cpu
->sibling
) {
368 if (cpu
->path
.type
!= DEVICE_PATH_APIC
) {
371 #if CONFIG_SERIAL_CPU_INIT == 0
381 if (cpu
->initialized
) {
385 if (!start_cpu(cpu
)) {
386 /* Record the error in cpu? */
387 printk(BIOS_ERR
, "CPU 0x%02x would not start!\n",
388 cpu
->path
.apic
.apic_id
);
390 #if CONFIG_SERIAL_CPU_INIT == 1
391 #if CONFIG_MAX_CPUS>2
399 static void wait_other_cpus_stop(struct bus
*cpu_bus
)
402 int old_active_count
, active_count
;
403 /* Now loop until the other cpus have finished initializing */
404 old_active_count
= 1;
405 active_count
= atomic_read(&active_cpus
);
406 while(active_count
> 1) {
407 if (active_count
!= old_active_count
) {
408 printk(BIOS_INFO
, "Waiting for %d CPUS to stop\n", active_count
- 1);
409 old_active_count
= active_count
;
412 active_count
= atomic_read(&active_cpus
);
414 for(cpu
= cpu_bus
->children
; cpu
; cpu
= cpu
->sibling
) {
415 if (cpu
->path
.type
!= DEVICE_PATH_APIC
) {
418 if (!cpu
->initialized
) {
419 printk(BIOS_ERR
, "CPU 0x%02x did not initialize!\n",
420 cpu
->path
.apic
.apic_id
);
423 printk(BIOS_DEBUG
, "All AP CPUs stopped\n");
426 #else /* CONFIG_SMP */
427 #define initialize_other_cpus(root) do {} while(0)
428 #endif /* CONFIG_SMP */
430 void initialize_cpus(struct bus
*cpu_bus
)
432 struct device_path cpu_path
;
433 struct cpu_info
*info
;
435 /* Find the info struct for this cpu */
439 /* Ensure the local apic is enabled */
442 /* Get the device path of the boot cpu */
443 cpu_path
.type
= DEVICE_PATH_APIC
;
444 cpu_path
.apic
.apic_id
= lapicid();
446 /* Get the device path of the boot cpu */
447 cpu_path
.type
= DEVICE_PATH_CPU
;
451 /* Find the device structure for the boot cpu */
452 info
->cpu
= alloc_find_dev(cpu_bus
, &cpu_path
);
455 copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
458 #if CONFIG_HAVE_SMI_HANDLER
462 cpus_ready_for_init();
465 #if CONFIG_SERIAL_CPU_INIT == 0
466 /* start all aps at first, so we can init ECC all together */
467 start_other_cpus(cpu_bus
, info
->cpu
);
471 /* Initialize the bootstrap processor */
475 #if CONFIG_SERIAL_CPU_INIT == 1
476 start_other_cpus(cpu_bus
, info
->cpu
);
479 /* Now wait the rest of the cpus stop*/
480 wait_other_cpus_stop(cpu_bus
);