2 * This file is part of the coreboot project.
4 * Copyright (C) 2018 Intel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <arch/acpi.h>
17 #include "variant/ec.h"
18 #include "variant/gpio.h"
23 0x02, // DSDT revision
26 0x20110725 // OEM revision
29 // Some generic macros
30 #include <soc/intel/icelake/acpi/platform.asl>
32 // global NVS and variables
33 #include <soc/intel/icelake/acpi/globalnvs.asl>
36 #include <cpu/intel/common/acpi/cpu.asl>
41 #include <soc/intel/icelake/acpi/northbridge.asl>
42 #include <soc/intel/icelake/acpi/southbridge.asl>
46 #if IS_ENABLED(CONFIG_CHROMEOS)
48 #include <vendorcode/google/chromeos/acpi/chromeos.asl>
51 // Chipset specific sleep states
52 #include <soc/intel/icelake/acpi/sleepstates.asl>
54 /* Chrome OS Embedded Controller */
55 Scope (\_SB.PCI0.LPCB)
57 /* ACPI code for EC SuperIO functions */
58 #include <ec/google/chromeec/acpi/superio.asl>
59 /* ACPI code for EC functions */
60 #include <ec/google/chromeec/acpi/ec.asl>