util/msrtool/intel_core2_early.c

   1 /*
   2  * This file is part of msrtool.
   3  *
   4  * Copyright (C) 2011 Anton Kochkov <anton.kochkov@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include "msrtool.h"
  17
  18 int intel_core2_early_probe(const struct targetdef *target, const struct cpuid_t *id) {
  19         return ((0x6 == id->family) && (0xf == id->model));
  20 }
  21
  22 const struct msrdef intel_core2_early_msrs[] = {
  23         {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
  24                 { BITS_EOT }
  25         }},
  26         {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", {
  27                 { BITS_EOT }
  28         }},
  29         {0x3f, MSRTYPE_RDWR, MSR2(0,0), "IA32_TEMPERATURE_OFFSET", "", {
  30                 { BITS_EOT }
  31         }},
  32         {0xa8, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE0", "", {
  33                 { BITS_EOT }
  34         }},
  35         {0xa9, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE1", "", {
  36                 { BITS_EOT }
  37         }},
  38         {0xaa, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE2", "", {
  39                 { BITS_EOT }
  40         }},
  41         {0xab, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE3", "", {
  42                 { BITS_EOT }
  43         }},
  44         {0xac, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE4", "", {
  45                 { BITS_EOT }
  46         }},
  47         {0xad, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE5", "", {
  48                 { BITS_EOT }
  49         }},
  50         {0xcd, MSRTYPE_RDWR, MSR2(0,0), "FSB_CLOCK_STS", "", {
  51                 { BITS_EOT }
  52         }},
  53         {0xe2, MSRTYPE_RDWR, MSR2(0,0), "PMG_CST_CONFIG_CONTROL", "", {
  54                 { BITS_EOT }
  55         }},
  56         {0xe3, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_BASE_ADDR", "", {
  57                 { BITS_EOT }
  58         }},
  59         {0xe4, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_CAPTURE_ADDR", "", {
  60                 { BITS_EOT }
  61         }},
  62         {0xee, MSRTYPE_RDWR, MSR2(0,0), "EXT_CONFIG", "", {
  63                 { BITS_EOT }
  64         }},
  65         {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", {
  66                 { BITS_EOT }
  67         }},
  68         {0x194, MSRTYPE_RDWR, MSR2(0,0), "CLOCK_FLEX_MAX", "", {
  69                 { BITS_EOT }
  70         }},
  71         {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
  72                 { BITS_EOT }
  73         }},
  74         {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", {
  75                 { BITS_EOT }
  76         }},
  77         {0x1aa, MSRTYPE_RDWR, MSR2(0,0), "PIC_SENS_CFG", "", {
  78                 { BITS_EOT }
  79         }},
  80         {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
  81                 { BITS_EOT }
  82         }},
  83         {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
  84                 { BITS_EOT }
  85         }},
  86         {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
  87                 { BITS_EOT }
  88         }},
  89         {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
  90                 { BITS_EOT }
  91         }},
  92         {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
  93                 { BITS_EOT }
  94         }},
  95         {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
  96                 { BITS_EOT }
  97         }},
  98         {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
  99                 { BITS_EOT }
 100         }},
 101         {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
 102                 { BITS_EOT }
 103         }},
 104         {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", {
 105                 { BITS_EOT }
 106         }},
 107         {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
 108                 { BITS_EOT }
 109         }},
 110         {0xe1, MSRTYPE_RDWR, MSR2(0,0), "SMM_CST_MISC_INFO", "", {
 111                 { BITS_EOT }
 112         }},
 113         {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", {
 114                 { BITS_EOT }
 115         }},
 116         {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", {
 117                 { BITS_EOT }
 118         }},
 119         {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
 120                 { BITS_EOT }
 121         }},
 122         {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
 123                 { BITS_EOT }
 124         }},
 125         {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
 126                 { BITS_EOT }
 127         }},
 128         {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CONTROL", "", {
 129                 { BITS_EOT }
 130         }},
 131         {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_CTL", "", {
 132                 { BITS_EOT }
 133         }},
 134         {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", {
 135                 { BITS_EOT }
 136         }},
 137         {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", {
 138                 { BITS_EOT }
 139         }},
 140         {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", {
 141                 { BITS_EOT }
 142         }},
 143         {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", {
 144                 { BITS_EOT }
 145         }},
 146         {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
 147                 { BITS_EOT }
 148         }},
 149         {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
 150                 { BITS_EOT }
 151         }},
 152         {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
 153                 { BITS_EOT }
 154         }},
 155         {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
 156                 { BITS_EOT }
 157         }},
 158         {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
 159                 { BITS_EOT }
 160         }},
 161         {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
 162                 { BITS_EOT }
 163         }},
 164         {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
 165                 { BITS_EOT }
 166         }},
 167         {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
 168                 { BITS_EOT }
 169         }},
 170         {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
 171                 { BITS_EOT }
 172         }},
 173         {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
 174                 { BITS_EOT }
 175         }},
 176         {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
 177                 { BITS_EOT }
 178         }},
 179         {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
 180                 { BITS_EOT }
 181         }},
 182         {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
 183                 { BITS_EOT }
 184         }},
 185         {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
 186                 { BITS_EOT }
 187         }},
 188         {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
 189                 { BITS_EOT }
 190         }},
 191         {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
 192                 { BITS_EOT }
 193         }},
 194         {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
 195                 { BITS_EOT }
 196         }},
 197         {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
 198                 { BITS_EOT }
 199         }},
 200         {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
 201                 { BITS_EOT }
 202         }},
 203         {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
 204                 { BITS_EOT }
 205         }},
 206         {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
 207                 { BITS_EOT }
 208         }},
 209         {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
 210                 { BITS_EOT }
 211         }},
 212         {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
 213                 { BITS_EOT }
 214         }},
 215         {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
 216                 { BITS_EOT }
 217         }},
 218         {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
 219                 { BITS_EOT }
 220         }},
 221         {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
 222                 { BITS_EOT }
 223         }},
 224         {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
 225                 { BITS_EOT }
 226         }},
 227         {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
 228                 { BITS_EOT }
 229         }},
 230         { MSR_EOT }
 231 };