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tree: drop last paragraph of GPL copyright header
[coreboot.git] / util / msrtool / geodegx2.c
blob9b6f221591a8b35c2eb2aff975b1b10c1a42bde5
1 /*
2 * This file is part of msrtool.
3 *
4 * Copyright (c) 2008 Peter Stuge <peter@stuge.se>
5 * Copyright (c) 2009 Nils Jacobs <njacobs8@hetnet.nl>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include "msrtool.h"
18
19 int geodegx2_probe(const struct targetdef *target, const struct cpuid_t *id) {
20 return 5 == id->family && 5 == id->model;
21 }
22
23 const struct msrdef geodegx2_msrs[] = {
24 { 0x10000020, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM0", "GLIU0 P2D Base Mask Descriptor 0", {
25 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
26 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
27 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
28 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
29 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
30 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
31 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
32 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
33 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
34 { BITVAL_EOT }
35 }},
36 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
37 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
38 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
39 { BITVAL_EOT }
40 }},
41 { 59, 20, RESERVED },
42 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
43 { BITVAL_EOT }
44 }},
45 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
46 { BITVAL_EOT }
47 }},
48 { BITS_EOT }
49 }},
50 { 0x10000021, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM1", "GLIU0 P2D Base Mask Descriptor 1", {
51 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
52 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
53 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
54 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
55 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
56 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
57 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
58 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
59 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
60 { BITVAL_EOT }
61 }},
62 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
63 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
64 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
65 { BITVAL_EOT }
66 }},
67 { 59, 20, RESERVED },
68 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
69 { BITVAL_EOT }
70 }},
71 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
72 { BITVAL_EOT }
73 }},
74 { BITS_EOT }
75 }},
76 { 0x10000022, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM2", "GLIU0 P2D Base Mask Descriptor 2", {
77 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
78 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
79 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
80 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
81 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
82 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
83 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
84 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
85 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
86 { BITVAL_EOT }
87 }},
88 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
89 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
90 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
91 { BITVAL_EOT }
92 }},
93 { 59, 20, RESERVED },
94 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
95 { BITVAL_EOT }
96 }},
97 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
98 { BITVAL_EOT }
99 }},
100 { BITS_EOT }
101 }},
102 { 0x10000023, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM3", "GLIU0 P2D Base Mask Descriptor 3", {
103 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
104 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
105 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
106 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
107 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
108 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
109 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
110 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
111 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
112 { BITVAL_EOT }
113 }},
114 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
115 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
116 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
117 { BITVAL_EOT }
118 }},
119 { 59, 20, RESERVED },
120 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
121 { BITVAL_EOT }
122 }},
123 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
124 { BITVAL_EOT }
125 }},
126 { BITS_EOT }
127 }},
128 { 0x10000024, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM4", "GLIU0 P2D Base Mask Descriptor 4", {
129 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
130 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
131 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
132 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
133 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
134 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
135 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
136 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
137 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
138 { BITVAL_EOT }
139 }},
140 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
141 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
142 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
143 { BITVAL_EOT }
144 }},
145 { 59, 20, RESERVED },
146 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
147 { BITVAL_EOT }
148 }},
149 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
150 { BITVAL_EOT }
151 }},
152 { BITS_EOT }
153 }},
154 { 0x10000025, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM5", "GLIU0 P2D Base Mask Descriptor 5", {
155 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
156 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
157 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
158 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
159 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
160 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
161 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
162 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
163 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
164 { BITVAL_EOT }
165 }},
166 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
167 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
168 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
169 { BITVAL_EOT }
170 }},
171 { 59, 20, RESERVED },
172 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
173 { BITVAL_EOT }
174 }},
175 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
176 { BITVAL_EOT }
177 }},
178 { BITS_EOT }
179 }},
180 { 0x10000026, MSRTYPE_RDWR, MSR2(0x00000FF0, 0xFFF00000), "GLIU0_P2D_BMO0", "GLIU0 P2D Base Mask Offset Descriptor 0", {
181 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
182 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
183 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
184 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
185 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
186 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
187 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
188 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
189 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
190 { BITVAL_EOT }
191 }},
192 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
193 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
194 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
195 { BITVAL_EOT }
196 }},
197 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, {
198 { BITVAL_EOT }
199 }},
200 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
201 { BITVAL_EOT }
202 }},
203 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
204 { BITVAL_EOT }
205 }},
206 { BITS_EOT }
207 }},
208 { 0x10000027, MSRTYPE_RDWR, MSR2(0x00000FF0, 0xFFF00000), "GLIU0_P2D_BMO1", "GLIU0 P2D Base Mask Offset Descriptor 1", {
209 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
210 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
211 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
212 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
213 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
214 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
215 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
216 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
217 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
218 { BITVAL_EOT }
219 }},
220 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
221 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
222 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
223 { BITVAL_EOT }
224 }},
225 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, {
226 { BITVAL_EOT }
227 }},
228 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
229 { BITVAL_EOT }
230 }},
231 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
232 { BITVAL_EOT }
233 }},
234 { BITS_EOT }
235 }},
236 { 0x10000028, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_R0", "GLIU0 P2D Range Descriptor 0", {
237 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
238 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
239 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
240 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
241 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
242 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
243 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
244 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
245 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
246 { BITVAL_EOT }
247 }},
248 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
249 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
250 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
251 { BITVAL_EOT }
252 }},
253 { 59, 20, RESERVED },
254 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
255 { BITVAL_EOT }
256 }},
257 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
258 { BITVAL_EOT }
259 }},
260 { BITS_EOT }
261 }},
262 { 0x10000029, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_RO0", "GLIU0 P2D Range Offset Descriptor 0", {
263 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
264 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
265 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
266 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
267 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
268 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
269 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
270 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
271 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
272 { BITVAL_EOT }
273 }},
274 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
275 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
276 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
277 { BITVAL_EOT }
278 }},
279 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, {
280 { BITVAL_EOT }
281 }},
282 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
283 { BITVAL_EOT }
284 }},
285 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
286 { BITVAL_EOT }
287 }},
288 { BITS_EOT }
289 }},
290 { 0x1000002A, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_RO1", "GLIU0 P2D Range Offset Descriptor 1", {
291 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
292 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
293 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
294 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
295 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
296 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
297 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
298 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
299 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
300 { BITVAL_EOT }
301 }},
302 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
303 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
304 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
305 { BITVAL_EOT }
306 }},
307 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, {
308 { BITVAL_EOT }
309 }},
310 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
311 { BITVAL_EOT }
312 }},
313 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
314 { BITVAL_EOT }
315 }},
316 { BITS_EOT }
317 }},
318 { 0x1000002B, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_RO2", "GLIU0 P2D Range Offset Descriptor 2", {
319 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
320 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
321 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
322 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
323 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
324 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
325 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
326 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
327 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
328 { BITVAL_EOT }
329 }},
330 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
331 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
332 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
333 { BITVAL_EOT }
334 }},
335 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, {
336 { BITVAL_EOT }
337 }},
338 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
339 { BITVAL_EOT }
340 }},
341 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
342 { BITVAL_EOT }
343 }},
344 { BITS_EOT }
345 }},
346 { 0x1000002C, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_P2D_SC0", "GLIU0 P2D Swiss Cheese Descriptor 0", {
347 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
348 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
349 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
350 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
351 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
352 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
353 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
354 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
355 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
356 { BITVAL_EOT }
357 }},
358 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
359 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
360 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
361 { BITVAL_EOT }
362 }},
363 { 59, 12, RESERVED },
364 { 47, 16, "WEN", "Enable hits to the base for the ith 16K page for writes", PRESENT_HEX, {
365 { BITVAL_EOT }
366 }},
367 { 31, 16, "REN", "Enable hits to the base for the ith 16K page for ", PRESENT_HEX, {
368 { BITVAL_EOT }
369 }},
370 { 15, 2, RESERVED },
371 { 13, 14, "PSCBASE", "Physical Memory Address Base for hit", PRESENT_HEX, {
372 { BITVAL_EOT }
373 }},
374 { BITS_EOT }
375 }},
376 { 0x100000E0, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_IOD_BM0", "GLIU0 IOD Base Mask Descriptor 0", {
377 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
378 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
379 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
380 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
381 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
382 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
383 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
384 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
385 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
386 { BITVAL_EOT }
387 }},
388 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
389 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
390 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
391 { BITVAL_EOT }
392 }},
393 { 59, 20, RESERVED },
394 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
395 { BITVAL_EOT }
396 }},
397 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
398 { BITVAL_EOT }
399 }},
400 { BITS_EOT }
401 }},
402 { 0x100000E1, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_IOD_BM1", "GLIU0 IOD Base Mask Descriptor 1", {
403 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
404 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
405 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
406 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
407 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
408 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
409 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
410 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
411 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
412 { BITVAL_EOT }
413 }},
414 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
415 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
416 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
417 { BITVAL_EOT }
418 }},
419 { 59, 20, RESERVED },
420 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
421 { BITVAL_EOT }
422 }},
423 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
424 { BITVAL_EOT }
425 }},
426 { BITS_EOT }
427 }},
428 { 0x100000E2, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_IOD_BM2", "GLIU0 IOD Base Mask Descriptor 2", {
429 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
430 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
431 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
432 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
433 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
434 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
435 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
436 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
437 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
438 { BITVAL_EOT }
439 }},
440 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
441 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
442 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
443 { BITVAL_EOT }
444 }},
445 { 59, 20, RESERVED },
446 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
447 { BITVAL_EOT }
448 }},
449 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
450 { BITVAL_EOT }
451 }},
452 { BITS_EOT }
453 }},
454 { 0x100000E3, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC0", "GLIU0 IOD Swiss Cheese Descriptor 0", {
455 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
456 { BITVAL_EOT }
457 }},
458 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
459 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
460 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
461 { BITVAL_EOT }
462 }},
463 { 59, 28, RESERVED },
464 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
465 { BITVAL_EOT }
466 }},
467 { 23, 2, RESERVED },
468 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
469 { BITVAL_EOT }
470 }},
471 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
472 { BITVAL_EOT }
473 }},
474 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
475 { BITVAL_EOT }
476 }},
477 { 2, 3, RESERVED },
478 { BITS_EOT }
479 }},
480 { 0x100000E4, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC1", "GLIU0 IOD Swiss Cheese Descriptor 1", {
481 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
482 { BITVAL_EOT }
483 }},
484 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
485 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
486 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
487 { BITVAL_EOT }
488 }},
489 { 59, 28, RESERVED },
490 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
491 { BITVAL_EOT }
492 }},
493 { 23, 2, RESERVED },
494 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
495 { BITVAL_EOT }
496 }},
497 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
498 { BITVAL_EOT }
499 }},
500 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
501 { BITVAL_EOT }
502 }},
503 { 2, 3, RESERVED },
504 { BITS_EOT }
505 }},
506 { 0x100000E5, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC2", "GLIU0 IOD Swiss Cheese Descriptor 2", {
507 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
508 { BITVAL_EOT }
509 }},
510 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
511 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
512 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
513 { BITVAL_EOT }
514 }},
515 { 59, 28, RESERVED },
516 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
517 { BITVAL_EOT }
518 }},
519 { 23, 2, RESERVED },
520 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
521 { BITVAL_EOT }
522 }},
523 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
524 { BITVAL_EOT }
525 }},
526 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
527 { BITVAL_EOT }
528 }},
529 { 2, 3, RESERVED },
530 { BITS_EOT }
531 }},
532 { 0x100000E6, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC3", "GLIU0 IOD Swiss Cheese Descriptor 3", {
533 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
534 { BITVAL_EOT }
535 }},
536 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
537 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
538 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
539 { BITVAL_EOT }
540 }},
541 { 59, 28, RESERVED },
542 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
543 { BITVAL_EOT }
544 }},
545 { 23, 2, RESERVED },
546 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
547 { BITVAL_EOT }
548 }},
549 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
550 { BITVAL_EOT }
551 }},
552 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
553 { BITVAL_EOT }
554 }},
555 { 2, 3, RESERVED },
556 { BITS_EOT }
557 }},
558 { 0x100000E7, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC4", "GLIU0 IOD Swiss Cheese Descriptor 4", {
559 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
560 { BITVAL_EOT }
561 }},
562 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
563 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
564 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
565 { BITVAL_EOT }
566 }},
567 { 59, 28, RESERVED },
568 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
569 { BITVAL_EOT }
570 }},
571 { 23, 2, RESERVED },
572 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
573 { BITVAL_EOT }
574 }},
575 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
576 { BITVAL_EOT }
577 }},
578 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
579 { BITVAL_EOT }
580 }},
581 { 2, 3, RESERVED },
582 { BITS_EOT }
583 }},
584 { 0x100000E8, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC5", "GLIU0 IOD Swiss Cheese Descriptor 5", {
585 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
586 { BITVAL_EOT }
587 }},
588 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
589 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
590 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
591 { BITVAL_EOT }
592 }},
593 { 59, 28, RESERVED },
594 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
595 { BITVAL_EOT }
596 }},
597 { 23, 2, RESERVED },
598 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
599 { BITVAL_EOT }
600 }},
601 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
602 { BITVAL_EOT }
603 }},
604 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
605 { BITVAL_EOT }
606 }},
607 { 2, 3, RESERVED },
608 { BITS_EOT }
609 }},
610 { 0x20000018, MSRTYPE_RDWR, MSR2(0x10071007, 0x40), "MC_CF07_DATA", "Refresh and SDRAM Program", {
611 { 63, 4, "D1_SZ", "DIMM1 Size", PRESENT_BIN, {
612 { MSR1(0), "Reserved" },
613 { MSR1(1), "8 MB" },
614 { MSR1(2), "16 MB" },
615 { MSR1(3), "32 MB" },
616 { MSR1(4), "64 MB" },
617 { MSR1(5), "128 MB" },
618 { MSR1(6), "256 MB" },
619 { MSR1(7), "512 MB" },
620 { MSR1(8), "Reserved" },
621 { MSR1(9), "Reserved" },
622 { MSR1(10), "Reserved" },
623 { MSR1(11), "Reserved" },
624 { MSR1(12), "Reserved" },
625 { MSR1(13), "Reserved" },
626 { MSR1(14), "Reserved" },
627 { MSR1(15), "Reserved" },
628 { BITVAL_EOT }
629 }},
630 { 59, 3, RESERVED },
631 { 56, 1, "D1_MB", "DIMM1 Module Banks", PRESENT_BIN, {
632 { MSR1(0), "1 Module bank" },
633 { MSR1(1), "2 Module banks" },
634 { BITVAL_EOT }
635 }},
636 { 55, 3, RESERVED },
637 { 52, 1, "D1_CB", "DIMM1 Component Banks", PRESENT_BIN, {
638 { MSR1(0), "2 Component banks" },
639 { MSR1(1), "4 Component banks" },
640 { BITVAL_EOT }
641 }},
642 { 51, 1, RESERVED },
643 { 50, 3, "D1_PSZ", "DIMM1 Page Size", PRESENT_BIN, {
644 { MSR1(0), "1 KB" },
645 { MSR1(1), "2 KB" },
646 { MSR1(2), "4 KB" },
647 { MSR1(3), "8 KB" },
648 { MSR1(4), "16 KB" },
649 { MSR1(5), "Reserved" },
650 { MSR1(6), "Reserved" },
651 { MSR1(7), "DIMM1 Not Installed" },
652 { BITVAL_EOT }
653 }},
654 { 47, 4, "D0_SZ", "DIMM0 Size", PRESENT_BIN, {
655 { MSR1(0), "Reserved" },
656 { MSR1(1), "8 MB" },
657 { MSR1(2), "16 MB" },
658 { MSR1(3), "32 MB" },
659 { MSR1(4), "64 MB" },
660 { MSR1(5), "128 MB" },
661 { MSR1(6), "256 MB" },
662 { MSR1(7), "512 MB" },
663 { MSR1(8), "Reserved" },
664 { MSR1(9), "Reserved" },
665 { MSR1(10), "Reserved" },
666 { MSR1(11), "Reserved" },
667 { MSR1(12), "Reserved" },
668 { MSR1(13), "Reserved" },
669 { MSR1(14), "Reserved" },
670 { MSR1(15), "Reserved" },
671 { BITVAL_EOT }
672 }},
673 { 43, 3, RESERVED },
674 { 40, 1, "D0_MB", "DIMM0 Module Banks", PRESENT_BIN, {
675 { MSR1(0), "1 Module bank" },
676 { MSR1(1), "2 Module banks" },
677 { BITVAL_EOT }
678 }},
679 { 39, 3, RESERVED },
680 { 36, 1, "D0_CB", "DIMM0 Component Banks", PRESENT_BIN, {
681 { MSR1(0), "2 Component banks" },
682 { MSR1(1), "4 Component banks" },
683 { BITVAL_EOT }
684 }},
685 { 35, 1, RESERVED },
686 { 34, 3, "D0_PSZ", "DIMM0 Page Size", PRESENT_BIN, {
687 { MSR1(0), "1 KB" },
688 { MSR1(1), "2 KB" },
689 { MSR1(2), "4 KB" },
690 { MSR1(3), "8 KB" },
691 { MSR1(4), "16 KB" },
692 { MSR1(5), "Reserved" },
693 { MSR1(6), "Reserved" },
694 { MSR1(7), "DIMM0 Not Installed" },
695 { BITVAL_EOT }
696 }},
697 { 31, 2, RESERVED },
698 { 29, 2, "EMR_BA", "Mode Register Set Bank Address", PRESENT_BIN, {
699 { MSR1(0), "Program the DIMM Mode Register" },
700 { MSR1(1), "Program the DIMM Extended Mode Register" },
701 { MSR1(2), "Reserved" },
702 { MSR1(3), "Reserved" },
703 { BITVAL_EOT }
704 }},
705 { 27, 1, RESERVED },
706 { 26, 1, "EMR_QFC", "Extended Mode Register FET Control", PRESENT_BIN, {
707 { MSR1(0), "Enable" },
708 { MSR1(1), "Disable" },
709 { BITVAL_EOT }
710 }},
711 { 25, 1, "EMR_DRV", "Extended Mode Register Drive Strength Control", PRESENT_BIN, {
712 { MSR1(0), "Normal" },
713 { MSR1(1), "Reduced" },
714 { BITVAL_EOT }
715 }},
716 { 24, 1, "EMR_DLL", "Extended Mode Register DLL", PRESENT_BIN, {
717 { MSR1(0), "Enable" },
718 { MSR1(1), "Disable" },
719 { BITVAL_EOT }
720 }},
721 { 23, 16, "REF_INT", "Refresh Interval", PRESENT_DEC, NOBITS },
722 { 7, 2, "REF_STAG", "Refresh Staggering", PRESENT_DEC, {
723 { MSR1(0), "4 SDRAM Clks" },
724 { MSR1(1), "1 SDRAM Clks" },
725 { MSR1(2), "2 SDRAM Clks" },
726 { MSR1(3), "3 SDRAM Clks" },
727 { BITVAL_EOT }
728 }},
729 { 5, 2, RESERVED },
730 { 3, 1, "REF_TST", "Test Refresh", PRESENT_BIN, NOBITS },
731 { 2, 1, RESERVED },
732 { 1, 1, "SOFT_RST", "Software Reset", PRESENT_BIN, NOBITS },
733 { 0, 1, "PROG_DRAM", "Program Mode Register in SDRAM", PRESENT_BIN, NOBITS },
734 { BITS_EOT }
735 }},
736 { 0x20000019, MSRTYPE_RDWR, MSR2(0x18000008, 0x287337a3), "MC_CF8F_DATA", "Timing and Mode Program", {
737 { 63, 8, "STALE_REQ", "GLIU Max Stale Request Count", PRESENT_DEC, NOBITS },
738 { 55, 3, RESERVED },
739 { 52, 2, "XOR_BIT_SEL", "XOR Bit Select", PRESENT_BIN, {
740 { MSR1(0), "ADDR[18]" },
741 { MSR1(1), "ADDR[19]" },
742 { MSR1(2), "ADDR[20]" },
743 { MSR1(3), "ADDR[21]" },
744 { BITVAL_EOT }
745 }},
746 { 50, 1, "XOR_MB0", "XOR MB0 Enable", PRESENT_BIN, {
747 { MSR1(0), "Disabled" },
748 { MSR1(1), "Enabled" },
749 { BITVAL_EOT }
750 }},
751 { 49, 1, "XOR_BA1", "XOR BA1 Enable", PRESENT_BIN, {
752 { MSR1(0), "Disabled" },
753 { MSR1(1), "Enabled" },
754 { BITVAL_EOT }
755 }},
756 { 48, 1, "XOR_BA0", "XOR BA0 Enable", PRESENT_BIN, {
757 { MSR1(0), "Disabled" },
758 { MSR1(1), "Enabled" },
759 { BITVAL_EOT }
760 }},
761 { 47, 8, RESERVED },
762 { 39, 1, "AP_B2B", "Autoprecharge Back-to-Back Command", PRESENT_BIN, {
763 { MSR1(0), "Enable" },
764 { MSR1(1), "Disable" },
765 { BITVAL_EOT }
766 }},
767 { 38, 1, "AP_EN", "Autoprecharge", PRESENT_BIN, {
768 { MSR1(0), "Enable" },
769 { MSR1(1), "Disable" },
770 { BITVAL_EOT }
771 }},
772 { 37, 4, RESERVED },
773 { 33, 1, "HOI_LOI", "High / Low Order Interleave Select", PRESENT_BIN, {
774 { MSR1(0), "Low Order Interleave" },
775 { MSR1(1), "High Order Interleave" },
776 { BITVAL_EOT }
777 }},
778 { 32, 1, RESERVED },
779 { 31, 1, "THZ_DLY", "tHZ Delay", PRESENT_BIN, NOBITS },
780 { 30, 3, "CAS_LAT", "Read CAS Latency", PRESENT_BIN, {
781 { MSR1(0), "Reserved" },
782 { MSR1(1), "Reserved" },
783 { MSR1(2), "2 Clks" },
784 { MSR1(3), "Reserved" },
785 { MSR1(4), "Reserved" },
786 { MSR1(5), "1.5 Clks" },
787 { MSR1(6), "2.5 Clks" },
788 { MSR1(7), "Reserved" },
789 { BITVAL_EOT }
790 }},
791 { 27, 4, "REF2ACT", "ACT to ACT/REF Period. tRC", PRESENT_BIN, {
792 { MSR1(0), "Reserved" },
793 { MSR1(1), "1 Clks" },
794 { MSR1(2), "2 Clks" },
795 { MSR1(3), "3 Clks" },
796 { MSR1(4), "4 Clks" },
797 { MSR1(5), "5 Clks" },
798 { MSR1(6), "7 Clks" },
799 { MSR1(7), "8 Clks" },
800 { MSR1(8), "9 Clks" },
801 { MSR1(9), "10 Clks" },
802 { MSR1(10), "11 Clks" },
803 { MSR1(11), "12 Clks" },
804 { MSR1(12), "13 Clks" },
805 { MSR1(13), "14 Clks" },
806 { MSR1(14), "15 Clks" },
807 { MSR1(15), "16 Clks" },
808 { BITVAL_EOT }
809 }},
810 { 23, 4, "ACT2PRE", "ACT to PRE Period. tRAS", PRESENT_BIN, {
811 { MSR1(0), "Reserved" },
812 { MSR1(1), "1 Clks" },
813 { MSR1(2), "2 Clks" },
814 { MSR1(3), "3 Clks" },
815 { MSR1(4), "4 Clks" },
816 { MSR1(5), "5 Clks" },
817 { MSR1(6), "7 Clks" },
818 { MSR1(7), "8 Clks" },
819 { MSR1(8), "9 Clks" },
820 { MSR1(9), "10 Clks" },
821 { MSR1(10), "11 Clks" },
822 { MSR1(11), "12 Clks" },
823 { MSR1(12), "13 Clks" },
824 { MSR1(13), "14 Clks" },
825 { MSR1(14), "15 Clks" },
826 { MSR1(15), "16 Clks" },
827 { BITVAL_EOT }
828 }},
829 { 19, 1, RESERVED },
830 { 18, 3, "PRE2ACT", "PRE to ACT Period. tRP", PRESENT_BIN, {
831 { MSR1(0), "Reserved" },
832 { MSR1(1), "1 Clks" },
833 { MSR1(2), "2 Clks" },
834 { MSR1(3), "3 Clks" },
835 { MSR1(4), "4 Clks" },
836 { MSR1(5), "5 Clks" },
837 { MSR1(6), "6 Clks" },
838 { MSR1(7), "7 Clks" },
839 { BITVAL_EOT }
840 }},
841 { 15, 1, RESERVED },
842 { 14, 3, "ACT2CMD", "Delay Time from ACT to Read/Write. tRCD", PRESENT_BIN, {
843 { MSR1(0), "Reserved" },
844 { MSR1(1), "1 Clks" },
845 { MSR1(2), "2 Clks" },
846 { MSR1(3), "3 Clks" },
847 { MSR1(4), "4 Clks" },
848 { MSR1(5), "5 Clks" },
849 { MSR1(6), "6 Clks" },
850 { MSR1(7), "Reserved" },
851 { BITVAL_EOT }
852 }},
853 { 11, 4, "ACT2ACT", "ACT(0) to ACT(1) Period. tRRD", PRESENT_BIN, {
854 { MSR1(0), "Reserved" },
855 { MSR1(1), "1 Clks" },
856 { MSR1(2), "2 Clks" },
857 { MSR1(3), "3 Clks" },
858 { MSR1(4), "4 Clks" },
859 { MSR1(5), "5 Clks" },
860 { MSR1(6), "6 Clks" },
861 { MSR1(7), "7 Clks" },
862 { MSR1(8), "Reserved" },
863 { MSR1(9), "Reserved" },
864 { MSR1(10), "Reserved" },
865 { MSR1(11), "Reserved" },
866 { MSR1(12), "Reserved" },
867 { MSR1(13), "Reserved" },
868 { MSR1(14), "Reserved" },
869 { MSR1(15), "Reserved" },
870 { BITVAL_EOT }
871 }},
872 { 7, 2, "DPLWR", "Data-in to PRE Period. tDPLW", PRESENT_DEC, {
873 { MSR1(0), "Invalid value" },
874 { MSR1(1), "1 Clks" },
875 { MSR1(2), "2 Clks" },
876 { MSR1(3), "3 Clks" },
877 { BITVAL_EOT }
878 }},
879 { 5, 2, "DPLRD", "Data-in to PRE Period. tDPLR", PRESENT_DEC, {
880 { MSR1(0), "Invalid value" },
881 { MSR1(1), "1 Clks" },
882 { MSR1(2), "2 Clks" },
883 { MSR1(3), "3 Clks" },
884 { BITVAL_EOT }
885 }},
886 { 3, 1, RESERVED },
887 { 2, 3, "DAL", "Data-in to ACT (REF) Period. tDAL", PRESENT_BIN, {
888 { MSR1(0), "Reserved" },
889 { MSR1(1), "1 clks" },
890 { MSR1(2), "2 Clks" },
891 { MSR1(3), "3 Clks" },
892 { MSR1(4), "4 Clks" },
893 { MSR1(5), "5 Clks" },
894 { MSR1(6), "6 Clks" },
895 { MSR1(7), "7 Clks" },
896 { BITVAL_EOT }
897 }},
898 { BITS_EOT }
899 }},
900 { 0x2000001a, MSRTYPE_RDWR, MSR2(0, 0), "MC_CF1017_DATA", "Feature Enables", {
901 { 63, 55, RESERVED },
902 { 8, 1, "PM1_UP_DLY", "PMode1 Up Delay", PRESENT_DEC, {
903 { MSR1(0), "No delay" },
904 { MSR1(1), "Enable delay" },
905 { BITVAL_EOT }
906 }},
907 { 7, 5, RESERVED },
908 { 2, 3, "WR2DAT", "Write Command to Data Latency", PRESENT_DEC, {
909 { MSR1(0), "Reserved" },
910 { MSR1(1), "Value when unbuffered DDR SDRAMs are used" },
911 { MSR1(2), "Value when registered DDR SDRAMs are used" },
912 { MSR1(3), "Reserved" },
913 { BITVAL_EOT }
914 }},
915 { BITS_EOT }
916 }},
917 { 0x2000001b, MSRTYPE_RDONLY, MSR2(0, 0), "MC_CFPERF_CNT1", "Performance Counters", {
918 { 63, 32, "CNT0", "Counter 0", PRESENT_DEC, NOBITS },
919 { 31, 32, "CNT1", "Counter 1", PRESENT_DEC, NOBITS },
920 { BITS_EOT }
921 }},
922 { 0x2000001c, MSRTYPE_RDWR, MSR2(0, 0x00ff00ff), "MC_PERFCNT2", "Counter and CAS Control", {
923 { 63, 28, RESERVED },
924 { 35, 1, "STOP_CNT1", "Stop Counter 1", PRESENT_DEC, {
925 { MSR1(0), "Counter 1 counts" },
926 { MSR1(1), "Stop Counter" },
927 { BITVAL_EOT }
928 }},
929 { 34, 1, "RST_CNT1", "Reset Counter 1", PRESENT_DEC, {
930 { MSR1(0), "Do nothing" },
931 { MSR1(1), "Reset counter 1" },
932 { BITVAL_EOT }
933 }},
934 { 33, 1, "STOP_CNT0", "Stop Counter 0", PRESENT_DEC, {
935 { MSR1(0), "Counter 0 counts" },
936 { MSR1(1), "Stop counter 0" },
937 { BITVAL_EOT }
938 }},
939 { 32, 1, "RST_CNT0", "Reset Counter 0", PRESENT_DEC, {
940 { MSR1(0), "Do nothing" },
941 { MSR1(1), "Reset counter 0" },
942 { BITVAL_EOT }
943 }},
944 { 31, 8, "CNT1_MASK", "Counter 1 Mask", PRESENT_BIN, NOBITS },
945 { 23, 8, "CNT1_DATA", "Counter 1 Data", PRESENT_BIN, NOBITS },
946 { 15, 8, "CNT0_MASK", "Counter 0 Mask", PRESENT_BIN, NOBITS },
947 { 7, 8, "CNT0_DATA", "Counter 0 Data", PRESENT_BIN, NOBITS },
948 { BITS_EOT }
949 }},
950 { 0x2000001d, MSRTYPE_RDWR, MSR2(0, 0x300), "MC_CFCLK_DBUG", "Clocking and Debug", {
951 { 63, 29, RESERVED },
952 { 34, 1, "B2B_EN", "Back-to-Back Command Enable", PRESENT_BIN, {
953 { MSR1(0), "Allow back-to-back commands" },
954 { MSR1(1), "Disable back-to-back commands" },
955 { BITVAL_EOT }
956 }},
957 { 33, 1, RESERVED },
958 { 32, 1, "MTEST_EN", "MTEST Enable", PRESENT_BIN, {
959 { MSR1(0), "Disable" },
960 { MSR1(1), "Enable" },
961 { BITVAL_EOT }
962 }},
963 { 31, 22, RESERVED },
964 { 9, 1, "MASK_CKE[1:0]", "CKE Mask", PRESENT_BIN, {
965 { MSR1(0), "CKE1 output enable unmasked" },
966 { MSR1(1), "CKE1 output enable masked" },
967 { BITVAL_EOT }
968 }},
969 { 8, 1, "MASK_CKE0", "CKE0 Mask", PRESENT_BIN, {
970 { MSR1(0), "CKE0 output enable unmasked" },
971 { MSR1(1), "CKE0 output enable masked" },
972 { BITVAL_EOT }
973 }},
974 { 7, 1, "CNTL_MSK1", "Control Mask 1", PRESENT_BIN, {
975 { MSR1(0), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable unmasked" },
976 { MSR1(1), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable masked" },
977 { BITVAL_EOT }
978 }},
979 { 6, 1, "CNTL_MSK0", "Control Mask 0", PRESENT_BIN, {
980 { MSR1(0), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable unmasked" },
981 { MSR1(1), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable masked" },
982 { BITVAL_EOT }
983 }},
984 { 5, 1, "ADRS_MSK", "Address Mask", PRESENT_BIN, {
985 { MSR1(0), "MA and BA output enable unmasked" },
986 { MSR1(1), "MA and BA output enable masked" },
987 { BITVAL_EOT }
988 }},
989 { 4, 5, RESERVED },
990 { BITS_EOT }
991 }},
992 { 0x40000020, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM0", "GLIU1 P2D Base Mask Descriptor 0", {
993 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
994 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
995 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
996 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
997 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
998 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
999 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1000 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1001 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1002 { BITVAL_EOT }
1003 }},
1004 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1005 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1006 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1007 { BITVAL_EOT }
1008 }},
1009 { 59, 20, RESERVED },
1010 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1011 { BITVAL_EOT }
1012 }},
1013 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1014 { BITVAL_EOT }
1015 }},
1016 { BITS_EOT }
1017 }},
1018 { 0x40000021, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM1", "GLIU1 P2D Base Mask Descriptor 1", {
1019 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1020 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1021 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1022 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1023 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1024 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1025 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1026 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1027 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1028 { BITVAL_EOT }
1029 }},
1030 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1031 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1032 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1033 { BITVAL_EOT }
1034 }},
1035 { 59, 20, RESERVED },
1036 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1037 { BITVAL_EOT }
1038 }},
1039 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1040 { BITVAL_EOT }
1041 }},
1042 { BITS_EOT }
1043 }},
1044 { 0x40000022, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM2", "GLIU1 P2D Base Mask Descriptor 2", {
1045 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1046 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1047 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1048 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1049 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1050 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1051 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1052 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1053 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1054 { BITVAL_EOT }
1055 }},
1056 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1057 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1058 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1059 { BITVAL_EOT }
1060 }},
1061 { 59, 20, RESERVED },
1062 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1063 { BITVAL_EOT }
1064 }},
1065 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1066 { BITVAL_EOT }
1067 }},
1068 { BITS_EOT }
1069 }},
1070 { 0x40000023, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM3", "GLIU1 P2D Base Mask Descriptor 3", {
1071 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1072 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1073 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1074 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1075 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1076 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1077 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1078 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1079 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1080 { BITVAL_EOT }
1081 }},
1082 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1083 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1084 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1085 { BITVAL_EOT }
1086 }},
1087 { 59, 20, RESERVED },
1088 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1089 { BITVAL_EOT }
1090 }},
1091 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1092 { BITVAL_EOT }
1093 }},
1094 { BITS_EOT }
1095 }},
1096 { 0x40000024, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM4", "GLIU1 P2D Base Mask Descriptor 4", {
1097 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1098 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1099 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1100 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1101 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1102 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1103 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1104 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1105 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1106 { BITVAL_EOT }
1107 }},
1108 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1109 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1110 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1111 { BITVAL_EOT }
1112 }},
1113 { 59, 20, RESERVED },
1114 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1115 { BITVAL_EOT }
1116 }},
1117 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1118 { BITVAL_EOT }
1119 }},
1120 { BITS_EOT }
1121 }},
1122 { 0x40000025, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM5", "GLIU1 P2D Base Mask Descriptor 5", {
1123 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1124 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1125 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1126 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1127 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1128 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1129 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1130 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1131 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1132 { BITVAL_EOT }
1133 }},
1134 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1135 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1136 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1137 { BITVAL_EOT }
1138 }},
1139 { 59, 20, RESERVED },
1140 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1141 { BITVAL_EOT }
1142 }},
1143 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1144 { BITVAL_EOT }
1145 }},
1146 { BITS_EOT }
1147 }},
1148 { 0x40000026, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM6", "GLIU1 P2D Base Mask Descriptor 6", {
1149 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1150 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1151 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1152 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1153 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1154 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1155 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1156 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1157 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1158 { BITVAL_EOT }
1159 }},
1160 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1161 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1162 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1163 { BITVAL_EOT }
1164 }},
1165 { 59, 20, RESERVED },
1166 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1167 { BITVAL_EOT }
1168 }},
1169 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1170 { BITVAL_EOT }
1171 }},
1172 { BITS_EOT }
1173 }},
1174 { 0x40000027, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM7", "GLIU1 P2D Base Mask Descriptor 7", {
1175 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1176 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1177 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1178 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1179 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1180 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1181 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1182 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1183 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1184 { BITVAL_EOT }
1185 }},
1186 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1187 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1188 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1189 { BITVAL_EOT }
1190 }},
1191 { 59, 20, RESERVED },
1192 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1193 { BITVAL_EOT }
1194 }},
1195 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1196 { BITVAL_EOT }
1197 }},
1198 { BITS_EOT }
1199 }},
1200 { 0x40000028, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM8", "GLIU1 P2D Base Mask Descriptor 8", {
1201 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1202 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1203 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1204 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1205 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1206 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1207 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1208 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1209 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1210 { BITVAL_EOT }
1211 }},
1212 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1213 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1214 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1215 { BITVAL_EOT }
1216 }},
1217 { 59, 20, RESERVED },
1218 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1219 { BITVAL_EOT }
1220 }},
1221 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1222 { BITVAL_EOT }
1223 }},
1224 { BITS_EOT }
1225 }},
1226 { 0x40000029, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU1_P2D_R0", "GLIU0 P2D Range Descriptor 0", {
1227 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1228 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1229 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1230 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1231 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1232 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1233 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1234 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1235 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1236 { BITVAL_EOT }
1237 }},
1238 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1239 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1240 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1241 { BITVAL_EOT }
1242 }},
1243 { 59, 20, RESERVED },
1244 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
1245 { BITVAL_EOT }
1246 }},
1247 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
1248 { BITVAL_EOT }
1249 }},
1250 { BITS_EOT }
1251 }},
1252 { 0x4000002A, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU1_P2D_R1", "GLIU0 P2D Range Descriptor 1", {
1253 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1254 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1255 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1256 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1257 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1258 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1259 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1260 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1261 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1262 { BITVAL_EOT }
1263 }},
1264 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1265 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1266 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1267 { BITVAL_EOT }
1268 }},
1269 { 59, 20, RESERVED },
1270 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
1271 { BITVAL_EOT }
1272 }},
1273 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
1274 { BITVAL_EOT }
1275 }},
1276 { BITS_EOT }
1277 }},
1278 { 0x4000002B, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_R2", "GLIU0 P2D Range Descriptor 2", {
1279 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1280 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1281 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1282 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1283 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1284 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1285 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1286 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1287 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1288 { BITVAL_EOT }
1289 }},
1290 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1291 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1292 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1293 { BITVAL_EOT }
1294 }},
1295 { 59, 20, RESERVED },
1296 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
1297 { BITVAL_EOT }
1298 }},
1299 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
1300 { BITVAL_EOT }
1301 }},
1302 { BITS_EOT }
1303 }},
1304 { 0x4000002C, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_R3", "GLIU0 P2D Range Descriptor 3", {
1305 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1306 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1307 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1308 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1309 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1310 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1311 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1312 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1313 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1314 { BITVAL_EOT }
1315 }},
1316 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1317 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1318 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1319 { BITVAL_EOT }
1320 }},
1321 { 59, 20, RESERVED },
1322 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
1323 { BITVAL_EOT }
1324 }},
1325 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
1326 { BITVAL_EOT }
1327 }},
1328 { BITS_EOT }
1329 }},
1330 { 0x4000002D, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_P2D_SC0", "GLIU1 P2D Swiss Cheese Descriptor 0", {
1331 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1332 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1333 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1334 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1335 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1336 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1337 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1338 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1339 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1340 { BITVAL_EOT }
1341 }},
1342 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1343 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1344 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1345 { BITVAL_EOT }
1346 }},
1347 { 59, 12, RESERVED },
1348 { 47, 16, "WEN", "Enable hits to the base for the ith 16K page for writes", PRESENT_HEX, {
1349 { BITVAL_EOT }
1350 }},
1351 { 31, 16, "REN", "Enable hits to the base for the ith 16K page for ", PRESENT_HEX, {
1352 { BITVAL_EOT }
1353 }},
1354 { 15, 2, RESERVED },
1355 { 13, 14, "PSCBASE", "Physical Memory Address Base for hit", PRESENT_HEX, {
1356 { BITVAL_EOT }
1357 }},
1358 { BITS_EOT }
1359 }},
1360 { 0x400000E0, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_IOD_BM0", "GLIU1 IOD Base Mask Descriptor 0", {
1361 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
1362 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1363 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1364 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1365 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1366 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1367 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1368 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1369 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1370 { BITVAL_EOT }
1371 }},
1372 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1373 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1374 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1375 { BITVAL_EOT }
1376 }},
1377 { 59, 20, RESERVED },
1378 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
1379 { BITVAL_EOT }
1380 }},
1381 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
1382 { BITVAL_EOT }
1383 }},
1384 { BITS_EOT }
1385 }},
1386 { 0x400000E1, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_IOD_BM1", "GLIU1 IOD Base Mask Descriptor 1", {
1387 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
1388 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1389 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1390 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1391 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1392 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1393 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1394 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1395 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1396 { BITVAL_EOT }
1397 }},
1398 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1399 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1400 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1401 { BITVAL_EOT }
1402 }},
1403 { 59, 20, RESERVED },
1404 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
1405 { BITVAL_EOT }
1406 }},
1407 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
1408 { BITVAL_EOT }
1409 }},
1410 { BITS_EOT }
1411 }},
1412 { 0x400000E2, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_IOD_BM2", "GLIU1 IOD Base Mask Descriptor 2", {
1413 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
1414 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1415 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1416 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1417 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1418 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1419 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1420 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1421 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1422 { BITVAL_EOT }
1423 }},
1424 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1425 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1426 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1427 { BITVAL_EOT }
1428 }},
1429 { 59, 20, RESERVED },
1430 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
1431 { BITVAL_EOT }
1432 }},
1433 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
1434 { BITVAL_EOT }
1435 }},
1436 { BITS_EOT }
1437 }},
1438 { 0x400000E3, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC0", "GLIU1 IOD Swiss Cheese Descriptor 0", {
1439 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1440 { BITVAL_EOT }
1441 }},
1442 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1443 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1444 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1445 { BITVAL_EOT }
1446 }},
1447 { 59, 28, RESERVED },
1448 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1449 { BITVAL_EOT }
1450 }},
1451 { 23, 2, RESERVED },
1452 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1453 { BITVAL_EOT }
1454 }},
1455 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1456 { BITVAL_EOT }
1457 }},
1458 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1459 { BITVAL_EOT }
1460 }},
1461 { 2, 3, RESERVED },
1462 { BITS_EOT }
1463 }},
1464 { 0x400000E4, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC1", "GLIU1 IOD Swiss Cheese Descriptor 1", {
1465 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1466 { BITVAL_EOT }
1467 }},
1468 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1469 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1470 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1471 { BITVAL_EOT }
1472 }},
1473 { 59, 28, RESERVED },
1474 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1475 { BITVAL_EOT }
1476 }},
1477 { 23, 2, RESERVED },
1478 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1479 { BITVAL_EOT }
1480 }},
1481 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1482 { BITVAL_EOT }
1483 }},
1484 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1485 { BITVAL_EOT }
1486 }},
1487 { 2, 3, RESERVED },
1488 { BITS_EOT }
1489 }},
1490 { 0x400000E5, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC2", "GLIU1 IOD Swiss Cheese Descriptor 2", {
1491 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1492 { BITVAL_EOT }
1493 }},
1494 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1495 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1496 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1497 { BITVAL_EOT }
1498 }},
1499 { 59, 28, RESERVED },
1500 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1501 { BITVAL_EOT }
1502 }},
1503 { 23, 2, RESERVED },
1504 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1505 { BITVAL_EOT }
1506 }},
1507 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1508 { BITVAL_EOT }
1509 }},
1510 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1511 { BITVAL_EOT }
1512 }},
1513 { 2, 3, RESERVED },
1514 { BITS_EOT }
1515 }},
1516 { 0x400000E6, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC3", "GLIU1 IOD Swiss Cheese Descriptor 3", {
1517 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1518 { BITVAL_EOT }
1519 }},
1520 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1521 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1522 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1523 { BITVAL_EOT }
1524 }},
1525 { 59, 28, RESERVED },
1526 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1527 { BITVAL_EOT }
1528 }},
1529 { 23, 2, RESERVED },
1530 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1531 { BITVAL_EOT }
1532 }},
1533 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1534 { BITVAL_EOT }
1535 }},
1536 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1537 { BITVAL_EOT }
1538 }},
1539 { 2, 3, RESERVED },
1540 { BITS_EOT }
1541 }},
1542 { 0x400000E7, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC4", "GLIU1 IOD Swiss Cheese Descriptor 4", {
1543 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1544 { BITVAL_EOT }
1545 }},
1546 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1547 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1548 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1549 { BITVAL_EOT }
1550 }},
1551 { 59, 28, RESERVED },
1552 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1553 { BITVAL_EOT }
1554 }},
1555 { 23, 2, RESERVED },
1556 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1557 { BITVAL_EOT }
1558 }},
1559 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1560 { BITVAL_EOT }
1561 }},
1562 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1563 { BITVAL_EOT }
1564 }},
1565 { 2, 3, RESERVED },
1566 { BITS_EOT }
1567 }},
1568 { 0x400000E8, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC5", "GLIU1 IOD Swiss Cheese Descriptor 5", {
1569 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1570 { BITVAL_EOT }
1571 }},
1572 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1573 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1574 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1575 { BITVAL_EOT }
1576 }},
1577 { 59, 28, RESERVED },
1578 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1579 { BITVAL_EOT }
1580 }},
1581 { 23, 2, RESERVED },
1582 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1583 { BITVAL_EOT }
1584 }},
1585 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1586 { BITVAL_EOT }
1587 }},
1588 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1589 { BITVAL_EOT }
1590 }},
1591 { 2, 3, RESERVED },
1592 { BITS_EOT }
1593 }},
1594 { 0x4c00000f, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_DELAY_CONTROLS", "GLCP I/O Delay Controls", {
1595 { 63, 1, "EN", "Delay Settings Enable", PRESENT_DEC, {
1596 { MSR1(0), "Use default values" },
1597 { MSR1(1), "Use value in bits [62:0]" },
1598 { BITVAL_EOT }
1599 }},
1600 { 62, 2, RESERVED },
1601 { 60, 5, "GIO", "Delay Geode Companion Device", PRESENT_DEC, NOBITS },
1602 { 55, 5, "PCI_IN", "Delay PCI Inputs", PRESENT_DEC, NOBITS },
1603 { 50, 5, "PCI_OUT", "Delay PCI Outputs", PRESENT_DEC, NOBITS },
1604 { 45, 5, RESERVED},
1605 { 40, 5, "DOTCLK", "Delay Dot Clock", PRESENT_DEC, NOBITS },
1606 { 35, 5, "DRGB", "Delay Digital RGBs", PRESENT_DEC, NOBITS },
1607 { 30, 5, "SDCLK_IN", "Delay SDRAM Clock Input", PRESENT_DEC, NOBITS },
1608 { 25, 5, "SDCLK_OUT", "Delay SDRAM Clock Output", PRESENT_DEC, NOBITS },
1609 { 20, 5, "MEM_CTL", "Delay Memory Controls", PRESENT_DEC, NOBITS },
1610 { 15, 9, RESERVED},
1611 { 6, 1, "MEM_ODDOUT", "Delay Odd Memory Data Output Bits", PRESENT_DEC, {
1612 { MSR1(0), "No Delay" },
1613 { MSR1(1), "Delay" },
1614 { BITVAL_EOT }
1615 }},
1616 { 5, 2, RESERVED },
1617 { 3, 2, "DQS_CLK_IN", "Delay DQS Before Clocking Input", PRESENT_DEC, NOBITS },
1618 { 1, 2, "DQS_CLK_OUT", "Delay DQS Before Clocking Output", PRESENT_DEC, NOBITS },
1619 { BITS_EOT }
1620 }},
1621 { 0x4c000014, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_SYS_RSTPLL", "GLCP System Reset and PLL Control", {
1622 { 63, 19, RESERVED },
1623 { 44, 4, "MDIV", "GLIU1 Divisor", PRESENT_BIN, {
1624 { MSR1(0), "Divide by 2" },
1625 { MSR1(1), "Divide by 3" },
1626 { MSR1(2), "Divide by 4" },
1627 { MSR1(3), "Divide by 5" },
1628 { MSR1(4), "Divide by 6" },
1629 { MSR1(5), "Divide by 7" },
1630 { MSR1(6), "Divide by 8" },
1631 { MSR1(7), "Divide by 9" },
1632 { MSR1(8), "Divide by 10" },
1633 { MSR1(9), "Divide by 11" },
1634 { MSR1(10), "Divide by 12" },
1635 { MSR1(11), "Divide by 13" },
1636 { MSR1(12), "Divide by 14" },
1637 { MSR1(13), "Divide by 15" },
1638 { MSR1(14), "Divide by 16" },
1639 { MSR1(15), "Divide by 17" },
1640 { BITVAL_EOT }
1641 }},
1642 { 40, 3, "VDIV", "CPU Core Divisor", PRESENT_BIN, {
1643 { MSR1(0), "Divide by 2" },
1644 { MSR1(1), "Divide by 3" },
1645 { MSR1(2), "Divide by 4" },
1646 { MSR1(3), "Divide by 5" },
1647 { MSR1(4), "Divide by 6" },
1648 { MSR1(5), "Divide by 7" },
1649 { MSR1(6), "Divide by 8" },
1650 { MSR1(7), "Divide by 9" },
1651 { BITVAL_EOT }
1652 }},
1653 { 37, 6, "FBDIV", "Feedback Devisor", PRESENT_DEC, NOBITS },
1654 { 31, 6, "SWFLAGS", "Software Flags", PRESENT_BIN, NOBITS },
1655 { 25, 1, "LOCK", "PLL Lock", PRESENT_DEC, {
1656 { MSR1(1), "PLL locked" },
1657 { MSR1(0), "PLL is not locked" },
1658 { BITVAL_EOT }
1659 }},
1660 { 24, 1, "LOCKWAIT", "Lock Wait", PRESENT_DEC, {
1661 { MSR1(0), "Disable" },
1662 { MSR1(1), "Enable" },
1663 { BITVAL_EOT }
1664 }},
1665 { 23, 8, "HOLD_COUNT", "Hold Count, divided by 16", PRESENT_DEC, NOBITS },
1666 { 15, 1, "BYPASS", "PLL Bypass", PRESENT_DEC, {
1667 { MSR1(0), "Use PLL as Clocksource" },
1668 { MSR1(1), "Use DOTREF as Clocksource" },
1669 { BITVAL_EOT }
1670 }},
1671 { 14, 1, "PD", "Power Down", PRESENT_DEC, {
1672 { MSR1(0), "PLL active" },
1673 { MSR1(1), "PLL in power down mode" },
1674 { BITVAL_EOT }
1675 }},
1676 { 13, 1, "RESETPLL", "PLL Reset", PRESENT_DEC, NOBITS },
1677 { 12, 2, RESERVED },
1678 { 10, 1, "DDRMODE", "DDR Mode", PRESENT_DEC, {
1679 { MSR1(0), "DDR communication enabled" },
1680 { MSR1(1), "Reserved" },
1681 { BITVAL_EOT }
1682 }},
1683 { 9, 1, "VA_SEMI_SYNC_MODE", "Synchronous CPU Core and GLIU1", PRESENT_DEC, {
1684 { MSR1(1), "CPU does not use GLIU1 FIFO" },
1685 { MSR1(0), "The GLIU1 FIFO is used by the CPU" },
1686 { BITVAL_EOT }
1687 }},
1688 { 8, 1, "PCI_SEMI_SYNC_MODE", "Synchronous CPU Core and GLIU1", PRESENT_DEC, {
1689 { MSR1(1), "PCI does not use mb_func_clk and pci_func_clk falling edges" },
1690 { MSR1(0), "Falling edges on mb_func_clk and pci_func_clk are used by PCI" },
1691 { BITVAL_EOT }
1692 }},
1693 { 7, 1, "DSTALL", "Debug Stall", PRESENT_DEC, NOBITS },
1694 { 6, 3, "BOOTSTRAP_STAT", "Bootstrap Status", PRESENT_BIN, NOBITS },
1695 { 3, 1, "DOTPOSTDIV3", "DOTPLL Post-Divide by 3", PRESENT_DEC, NOBITS },
1696 { 2, 1, "DOTPREMULT2", "DOTPLL Pre-Multiply by 2", PRESENT_DEC, NOBITS },
1697 { 1, 1, "DOTPREDIV2", "DOTPLL Pre-Divide by 2", PRESENT_DEC, NOBITS },
1698 { 0, 1, "CHIP_RESET", "Chip Reset", PRESENT_DEC, NOBITS },
1699 { BITS_EOT }
1700 }},
1701 { MSR_EOT }
1702 };
ast, secure and flexible OpenSource firmware