src/superio/winbond/w83627ehg/w83627ehg.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #ifndef SUPERIO_WINBOND_W83627EHG_H
  19 #define SUPERIO_WINBOND_W83627EHG_H
  20
  21 #define W83627EHG_FDC              0   /* Floppy */
  22 #define W83627EHG_PP               1   /* Parallel port */
  23 #define W83627EHG_SP1              2   /* Com1 */
  24 #define W83627EHG_SP2              3   /* Com2 */
  25 #define W83627EHG_KBC              5   /* PS/2 keyboard & mouse */
  26 #define W83627EHG_WDTO_PLED        8   /* Watchdog timer timeout, power LED */
  27 #define W83627EHG_ACPI            10   /* ACPI */
  28 #define W83627EHG_HWM             11   /* Hardware monitor */
  29
  30 /* The following are handled using "virtual LDNs" (hence the _V suffix). */
  31 #define W83627EHG_SFI_V            6   /* Serial flash interface (SFI) */
  32 #define W83627EHG_GPIO_GAME_MIDI_V 7   /* GPIO1, GPIO6, game port, MIDI */
  33 #define W83627EHG_GPIO_SUSLED_V    9   /* GPIO2, GPIO3, GPIO4, GPIO5, SUSLED */
  34
  35 /*
  36  * Virtual devices sharing the enables are encoded as follows:
  37  *   VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN
  38  */
  39
  40 /* SFI has bit 1 as enable (instead of bit 0 as usual). */
  41 #define W83627EHG_SFI   ((1 << 8) | W83627EHG_SFI_V)
  42
  43 #define W83627EHG_GPIO1 ((0 << 8) | W83627EHG_GPIO_GAME_MIDI_V)
  44 #define W83627EHG_GAME  ((1 << 8) | W83627EHG_GPIO_GAME_MIDI_V)
  45 #define W83627EHG_MIDI  ((2 << 8) | W83627EHG_GPIO_GAME_MIDI_V)
  46 #define W83627EHG_GPIO6 ((3 << 8) | W83627EHG_GPIO_GAME_MIDI_V)
  47
  48 #define W83627EHG_GPIO2 ((0 << 8) | W83627EHG_GPIO_SUSLED_V)
  49 #define W83627EHG_GPIO3 ((1 << 8) | W83627EHG_GPIO_SUSLED_V)
  50 #define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V)
  51 #define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V)
  52
  53 void pnp_enter_ext_func_mode(pnp_devfn_t dev);
  54 void pnp_exit_ext_func_mode(pnp_devfn_t dev);
  55
  56 #endif /* SUPERIO_WINBOND_W83627EHG_H */