src/superio/smsc/sio1036/sio1036_early_init.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */
  17
  18 #include <arch/io.h>
  19 #include <stdint.h>
  20
  21 #include "sio1036.h"
  22
  23 static inline void sio1036_enter_conf_state(pnp_devfn_t dev)
  24 {
  25         unsigned port = dev >> 8;
  26         outb(0x55, port);
  27 }
  28
  29 static inline void sio1036_exit_conf_state(pnp_devfn_t dev)
  30 {
  31         unsigned port = dev >> 8;
  32         outb(0xaa, port);
  33 }
  34
  35 /* Detect SMSC SIO1036 LPC Debug Card status */
  36 static u8 detect_sio1036_chip(unsigned port)
  37 {
  38         pnp_devfn_t dev = PNP_DEV(port, SIO1036_SP1);
  39         unsigned data;
  40
  41         sio1036_enter_conf_state (dev);
  42         data = pnp_read_config (dev, 0x0D);
  43         sio1036_exit_conf_state(dev);
  44
  45         /* Detect SMSC SIO1036 chip */
  46         if (data == 0x82) {
  47                 /* Found SMSC SIO1036 chip */
  48                 return 0;
  49         }
  50         else {
  51                 return 1;
  52         };
  53 }
  54
  55 void sio1036_enable_serial(pnp_devfn_t dev, u16 iobase)
  56 {
  57         unsigned port = dev >> 8;
  58
  59         if (detect_sio1036_chip(port) != 0)
  60                 return;
  61
  62         sio1036_enter_conf_state (dev);
  63
  64         /* Enable SMSC UART 0 */
  65         /* Valid configuration cycle */
  66         pnp_write_config (dev, 0x00, 0x28);
  67
  68         /* PP power/mode/cr lock */
  69         pnp_write_config (dev, 0x01, 0x98 | LPT_POWER_DOWN);
  70         pnp_write_config (dev, 0x02, 0x08 | UART_POWER_DOWN);
  71
  72         /*Auto power management*/
  73         pnp_write_config (dev, 0x07, 0x00 );
  74
  75         /*ECP FIFO threhod */
  76         pnp_write_config (dev, 0x0A, 0x00 | IR_OUPUT_MUX);
  77
  78         /*GPIO direction register 2 */
  79         pnp_write_config (dev, 0x033, 0x00);
  80
  81         /*UART Mode */
  82         pnp_write_config (dev, 0x0C, 0x02);
  83
  84         /* GPIO polarity regisgter 2 */
  85         pnp_write_config (dev, 0x034, 0x00);
  86
  87         /* Enable SMSC UART 0 */
  88         /*Set base io address */
  89         pnp_write_config (dev, 0x25, (u8)(iobase >> 2));
  90
  91         /* Set UART IRQ onto 0x04 */
  92         pnp_write_config (dev, 0x28, 0x04);
  93
  94         sio1036_exit_conf_state(dev);
  95 }