src/superio/smsc/sch4037/sch4037_early_init.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16
  17 #include <arch/io.h>
  18 #include <device/pnp.h>
  19 #include <stdint.h>
  20
  21 #include "sch4037.h"
  22
  23 static void pnp_enter_conf_state(pnp_devfn_t dev)
  24 {
  25         unsigned port = dev >> 8;
  26         outb(0x55, port);
  27 }
  28
  29 static void pnp_exit_conf_state(pnp_devfn_t dev)
  30 {
  31         unsigned port = dev >> 8;
  32         outb(0xaa, port);
  33 }
  34
  35 void sch4037_early_init(unsigned port)
  36 {
  37         pnp_devfn_t dev;
  38
  39         dev = PNP_DEV(port, SMSCSUPERIO_SP1);
  40         pnp_enter_conf_state(dev);
  41
  42         /* Auto power management */
  43         pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */
  44         pnp_write_config(dev, 0x23, 0 );
  45
  46         /* Enable SMSC UART 0 */
  47         dev = PNP_DEV(port, SMSCSUPERIO_SP1);
  48         pnp_set_logical_device(dev);
  49         pnp_set_enable(dev, 0);
  50
  51         pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
  52         pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4);
  53
  54         /* Enabled High speed, disabled MIDI support. */
  55         pnp_write_config(dev, 0xF0, 0x02);
  56         pnp_set_enable(dev, 1);
  57
  58         /* Enable keyboard */
  59         dev = PNP_DEV(port, SCH4037_KBC);
  60         pnp_set_logical_device(dev);
  61         pnp_set_enable(dev, 0);
  62         pnp_set_irq(dev, 0x70, 1);   /* IRQ 1 */
  63         pnp_set_irq(dev, 0x72, 12);   /* IRQ 12 */
  64         pnp_set_enable(dev, 1);
  65
  66         pnp_exit_conf_state(dev);
  67 }