2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #ifndef SUPERIO_INTEL_I3100_H
18 #define SUPERIO_INTEL_I3100_H
22 * - Name: Intel 3100 Chipset
23 * - URL: http://www.intel.com/design/intarch/datashts/313458.htm
24 * - PDF: http://download.intel.com/design/intarch/datashts/31345803.pdf
25 * - Revision / Date: 007, October 2008
26 * - Order number: 313458-007US
30 * The SIW ("Serial I/O and Watchdog Timer") integrated into the i3100 is
31 * very similar to a Super I/O, both in functionality and config mechanism.
35 * - Serial interrupt controller
36 * - Watchdog timer (WDT)
40 /* Logical device numbers (LDNs). */
41 #define I3100_SP1 0x04 /* Com1 */
42 #define I3100_SP2 0x05 /* Com2 */
43 #define I3100_WDT 0x06 /* Watchdog timer */
45 /* Registers and bit definitions: */
47 #define I3100_SIW_CONFIGURATION 0x29
50 * SIW_CONFIGURATION[3:2] = UART_CLK predivide
56 #define I3100_UART_CLK_PREDIVIDE_1 0x00
57 #define I3100_UART_CLK_PREDIVIDE_8 0x01
58 #define I3100_UART_CLK_PREDIVIDE_26 0x02
63 void i3100_configure_uart_clk(pnp_devfn_t dev
, u8 predivide
);
64 void i3100_enable_serial(pnp_devfn_t dev
, u16 iobase
);
66 #endif /* SUPERIO_INTEL_I3100_H */