src/southbridge/via/vt8237r/ide.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 /* Based on other VIA SB code. */
  17
  18 #include <device/device.h>
  19 #include <device/pci.h>
  20 #include <device/pci_ids.h>
  21 #include <console/console.h>
  22 #include "vt8237r.h"
  23 #include "chip.h"
  24
  25 /**
  26  * Cable type detect function, weak so it can be overloaded in mainboard.c
  27  */
  28 u32 __attribute__((weak)) vt8237_ide_80pin_detect(struct device *dev)
  29 {
  30         struct southbridge_via_vt8237r_config *sb =
  31             (struct southbridge_via_vt8237r_config *)dev->chip_info;
  32         u32 res;
  33         res  = sb->ide0_80pin_cable ? VT8237R_IDE0_80PIN_CABLE : 0;
  34         res |= sb->ide1_80pin_cable ? VT8237R_IDE1_80PIN_CABLE : 0;
  35         return res;
  36 }
  37
  38 /**
  39  * No native mode. Interrupts from unconnected HDDs might occur if
  40  * IRQ14/15 is used for PCI. Therefore no native mode support.
  41  */
  42 static void ide_init(struct device *dev)
  43 {
  44         struct southbridge_via_vt8237r_config *sb =
  45             (struct southbridge_via_vt8237r_config *)dev->chip_info;
  46
  47         u8 enables;
  48         u32 cablesel;
  49
  50         printk(BIOS_INFO, "%s IDE interface %s\n", "Primary",
  51                     sb->ide0_enable ? "enabled" : "disabled");
  52         printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary",
  53                     sb->ide1_enable ? "enabled" : "disabled");
  54         enables = pci_read_config8(dev, IDE_CS) & ~0x3;
  55         enables |= (sb->ide0_enable << 1) | sb->ide1_enable;
  56         pci_write_config8(dev, IDE_CS, enables);
  57         enables = pci_read_config8(dev, IDE_CS);
  58         printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables);
  59
  60         /* Enable only compatibility mode. */
  61         enables = pci_read_config8(dev, 0x09);
  62         enables &= 0xFA;
  63         pci_write_config8(dev, 0x09, enables);
  64
  65         enables = pci_read_config8(dev, IDE_CONF_II);
  66         enables &= ~0xc0;
  67         pci_write_config8(dev, IDE_CONF_II, enables);
  68         enables = pci_read_config8(dev, IDE_CONF_II);
  69         printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables);
  70
  71         /* Enable prefetch buffers. */
  72         enables = pci_read_config8(dev, IDE_CONF_I);
  73         enables |= 0xf0;
  74         pci_write_config8(dev, IDE_CONF_I, enables);
  75
  76         /* Flush FIFOs at half. */
  77         enables = pci_read_config8(dev, IDE_CONF_FIFO);
  78         enables &= 0xf0;
  79         enables |= (1 << 2) | (1 << 0);
  80         pci_write_config8(dev, IDE_CONF_FIFO, enables);
  81
  82         /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */
  83         enables = pci_read_config8(dev, IDE_MISC_I);
  84         enables &= 0xe2;
  85         enables |= (1 << 4) | (1 << 3);
  86         pci_write_config8(dev, IDE_MISC_I, enables);
  87
  88         /* Use memory read multiple, Memory-Write-and-Invalidate. */
  89         enables = pci_read_config8(dev, IDE_MISC_II);
  90         enables &= 0xEF;
  91         enables |= (1 << 2) | (1 << 3);
  92         pci_write_config8(dev, IDE_MISC_II, enables);
  93
  94         /* Force interrupts to use compat mode. */
  95         pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0);
  96         pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff);
  97
  98         /* Cable guy... */
  99         cablesel = pci_read_config32(dev, IDE_UDMA);
 100         cablesel &= ~VT8237R_IDE_CABLESEL_MASK;
 101         cablesel |= vt8237_ide_80pin_detect(dev);
 102         pci_write_config32(dev, IDE_UDMA, cablesel);
 103
 104 #if CONFIG_EPIA_VT8237R_INIT
 105         device_t lpc_dev;
 106
 107         /* Set PATA Output Drive Strength */
 108         lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
 109                                     PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
 110         if (lpc_dev)
 111                 pci_write_config8(lpc_dev, 0x7C, 0x20);
 112 #endif
 113 }
 114
 115 static const struct device_operations ide_ops = {
 116         .read_resources         = pci_dev_read_resources,
 117         .set_resources          = pci_dev_set_resources,
 118         .enable_resources       = pci_dev_enable_resources,
 119         .init                   = ide_init,
 120         .enable                 = 0,
 121         .ops_pci                = 0,
 122 };
 123
 124 static const struct pci_driver northbridge_driver __pci_driver = {
 125         .ops    = &ide_ops,
 126         .vendor = PCI_VENDOR_ID_VIA,
 127         .device = PCI_DEVICE_ID_VIA_82C586_1,
 128 };