src/southbridge/sis/sis966/sis966.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2004 Tyan Computer
   5  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   6  * Copyright (C) 2006,2007 AMD
   7  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
   8  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
   9  * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  */
  21
  22 #include <console/console.h>
  23
  24 #include <arch/io.h>
  25
  26 #include <device/device.h>
  27 #include <device/pci.h>
  28 #include <device/pci_ids.h>
  29 #include <device/pci_ops.h>
  30 #include "sis966.h"
  31
  32 static uint32_t final_reg;
  33
  34 static device_t find_lpc_dev( device_t dev,  unsigned devfn)
  35 {
  36
  37         device_t lpc_dev;
  38
  39         lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
  40
  41         if ( !lpc_dev ) return lpc_dev;
  42
  43 if ((lpc_dev->vendor != PCI_VENDOR_ID_SIS) || (
  44                 (lpc_dev->device != PCI_DEVICE_ID_SIS_SIS966_LPC)
  45                 ) ) {
  46                         uint32_t id;
  47                         id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
  48                         if ( (id < (PCI_VENDOR_ID_SIS | (PCI_DEVICE_ID_SIS_SIS966_LPC << 16)))
  49                                 ) {
  50                                 lpc_dev = 0;
  51                         }
  52         }
  53
  54         return lpc_dev;
  55 }
  56
  57 void sis966_enable(device_t dev)
  58 {
  59         device_t lpc_dev = 0;
  60         device_t sm_dev = 0;
  61         uint16_t index = 0;
  62         uint16_t index2 = 0;
  63         uint32_t reg_old, reg;
  64         uint8_t byte;
  65         uint16_t deviceid;
  66         uint16_t vendorid;
  67         uint16_t devfn;
  68
  69         struct southbridge_sis_sis966_config *conf;
  70         conf = dev->chip_info;
  71         int i;
  72
  73         if(dev->device==0x0000) {
  74                 vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
  75                 deviceid = (vendorid>>16) & 0xffff;
  76 //              vendorid &= 0xffff;
  77         } else {
  78 //              vendorid = dev->vendor;
  79                 deviceid = dev->device;
  80         }
  81
  82         devfn = (dev->path.pci.devfn) & ~7;
  83         switch(deviceid) {
  84                 case PCI_DEVICE_ID_SIS_SIS966_USB:
  85                         devfn -= (1<<3);
  86                         index = 8;
  87                         break;
  88                 case PCI_DEVICE_ID_SIS_SIS966_USB2:
  89                         devfn -= (1<<3);
  90                         index = 20;
  91                         break;
  92                 case PCI_DEVICE_ID_SIS_SIS966_NIC:
  93                         devfn -= (7<<3);
  94                         index = 10;
  95                         for(i=0;i<2;i++) {
  96                                 lpc_dev = find_lpc_dev(dev, devfn - (i<<3));
  97                                 if(!lpc_dev) continue;
  98                                 index -= i;
  99                                 devfn -= (i<<3);
 100                                 break;
 101                         }
 102                         break;
 103                 case PCI_DEVICE_ID_SIS_SIS966_HD_AUDIO:
 104                         devfn -= (5<<3);
 105                         index = 11;
 106                         break;
 107                 case PCI_DEVICE_ID_SIS_SIS966_IDE:
 108                         devfn -= (3<<3);
 109                         index = 14;
 110                         break;
 111                 case PCI_DEVICE_ID_SIS_SIS966_SATA:
 112                         devfn -= (4<<3);
 113                         index = 22;
 114                         i = (dev->path.pci.devfn) & 7;
 115                         if(i>0) {
 116                                 index -= (i+3);
 117                         }
 118                         break;
 119                 case PCI_DEVICE_ID_SIS_SIS966_PCIE:
 120                         devfn -= (0x9<<3);  // to LPC
 121                         index2 = 9;
 122                         break;
 123                 default:
 124                         index = 0;
 125         }
 126
 127         if(!lpc_dev)
 128                 lpc_dev = find_lpc_dev(dev, devfn);
 129
 130         if ( !lpc_dev ) return;
 131
 132         if(index2!=0) {
 133                 sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
 134                 if(!sm_dev) return;
 135
 136                 if ( sm_dev ) {
 137                         reg_old = reg =  pci_read_config32(sm_dev, 0xe4);
 138
 139                         if (!dev->enabled) { //disable it
 140                                 reg |= (1<<index2);
 141                         }
 142
 143                         if (reg != reg_old) {
 144                                 pci_write_config32(sm_dev, 0xe4, reg);
 145                         }
 146                 }
 147
 148                 index2 = 0;
 149                 return;
 150         }
 151
 152
 153         if ( index == 0) {  // for LPC
 154
 155                 // expose ioapic base
 156                 byte = pci_read_config8(lpc_dev, 0x74);
 157                 byte |= ((1<<1)); // expose the BAR
 158                 pci_write_config8(dev, 0x74, byte);
 159
 160                 // expose trap base
 161                 byte = pci_read_config8(lpc_dev, 0xdd);
 162                 byte |= ((1<<0)|(1<<3)); // expose the BAR and enable write
 163                 pci_write_config8(dev, 0xdd, byte);
 164                 return;
 165
 166         }
 167
 168         if( index == 16) {
 169                 sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
 170                 if(!sm_dev) return;
 171
 172                 final_reg = pci_read_config32(sm_dev, 0xe8);
 173                 final_reg &= ~0x0057cf00;
 174                 pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
 175         }
 176
 177         if (!dev->enabled) {
 178                 final_reg |= (1 << index);// disable it
 179                 /*
 180                  * The reason for using final_reg is that if func 1 is disabled,
 181                  * then func 2 will become func 1.
 182                  * Because of this, we need loop through disabling them all at
 183                  * the same time.
 184                  */
 185         }
 186
 187         if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8
 188                 sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
 189                 if(!sm_dev) return;
 190                 reg_old = pci_read_config32(sm_dev, 0xe8);
 191                 if (final_reg != reg_old) {
 192                         pci_write_config32(sm_dev, 0xe8, final_reg);
 193                 }
 194
 195         }
 196 }
 197
 198 struct chip_operations southbridge_sis_sis966_ops = {
 199         CHIP_NAME("SiS SiS966 Southbridge")
 200         .enable_dev     = sis966_enable,
 201 };