2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 AMD
5 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
6 * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
7 * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 void sis966_early_pcie_setup(unsigned busnx
, unsigned devnx
, unsigned anactrl_io_base
, unsigned pci_e_x
)
27 dev
= PCI_DEV(busnx
, devnx
+1, 1);
28 dword
= pci_read_config32(dev
, 0xe4);
29 dword
|= 0x3f0; // disable it at first
30 pci_write_config32(dev
, 0xe4, dword
);
33 tgio_ctrl
= inl(anactrl_io_base
+ 0xcc);
36 outl(tgio_ctrl
, anactrl_io_base
+ 0xcc);
37 pll_ctrl
= inl(anactrl_io_base
+ 0x30);
39 outl(pll_ctrl
, anactrl_io_base
+ 0x30);
41 pll_ctrl
= inl(anactrl_io_base
+ 0x30);
42 } while (!(pll_ctrl
& 1));
44 tgio_ctrl
= inl(anactrl_io_base
+ 0xcc);
45 tgio_ctrl
&= ~((7<<4)|(1<<8));
46 tgio_ctrl
|= (pci_e_x
<<4)|(1<<8);
47 outl(tgio_ctrl
, anactrl_io_base
+ 0xcc);
52 dword
= pci_read_config32(dev
, 0xe4);
53 dword
&= ~(0x3f0); // enable
54 pci_write_config32(dev
, 0xe4, dword
);