src/southbridge/nvidia/mcp55/pci.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2004 Tyan Computer
   5  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   6  * Copyright (C) 2006,2007 AMD
   7  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #include <console/console.h>
  21 #include <device/device.h>
  22 #include <device/resource.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25 #include <device/pci_ops.h>
  26 #include "mcp55.h"
  27
  28 static void pci_init(struct device *dev)
  29 {
  30         u32 dword;
  31         u16 word;
  32         device_t pci_domain_dev;
  33         struct resource *mem, *pref;
  34
  35         /* System error enable */
  36         dword = pci_read_config32(dev, 0x04);
  37         dword |= (1<<8); /* System error enable */
  38         dword |= (1<<30); /* Clear possible errors */
  39         pci_write_config32(dev, 0x04, dword);
  40
  41 #if 1
  42         //only need (a01,xx]
  43         word = pci_read_config16(dev, 0x48);
  44         word |= (1<<0); /* MRL2MRM */
  45         word |= (1<<2); /* MR2MRM */
  46         pci_write_config16(dev, 0x48, word);
  47 #endif
  48
  49 #if 1
  50         dword = pci_read_config32(dev, 0x4c);
  51         dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/
  52         pci_write_config32(dev, 0x4c, dword);
  53 #endif
  54
  55         pci_domain_dev = dev->bus->dev;
  56         while (pci_domain_dev) {
  57                 if (pci_domain_dev->path.type == DEVICE_PATH_DOMAIN)
  58                         break;
  59                 pci_domain_dev = pci_domain_dev->bus->dev;
  60         }
  61
  62         if (!pci_domain_dev)
  63                 return;         /* Impossible */
  64
  65         pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0));
  66         mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0));
  67
  68         if (!mem)
  69                 return;         /* Impossible */
  70
  71         if (!pref || pref->base > mem->base) {
  72                 dword = mem->base & (0xffff0000UL);
  73                 printk(BIOS_DEBUG, "PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
  74         } else {
  75                 dword = pref->base & (0xffff0000UL);
  76                 printk(BIOS_DEBUG, "PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
  77         }
  78
  79         printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword);
  80         pci_write_config32(dev, 0x50, dword);   /* TOM */
  81 }
  82
  83 static struct device_operations pci_ops  = {
  84         .read_resources = pci_bus_read_resources,
  85         .set_resources  = pci_dev_set_resources,
  86         .enable_resources       = pci_bus_enable_resources,
  87         .init           = pci_init,
  88         .scan_bus       = pci_scan_bridge,
  89 //      .enable         = mcp55_enable,
  90         .reset_bus      = pci_bus_reset,
  91 };
  92
  93 static const struct pci_driver pci_driver __pci_driver = {
  94         .ops    = &pci_ops,
  95         .vendor = PCI_VENDOR_ID_NVIDIA,
  96         .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCI,
  97 };