src/southbridge/intel/sch/ide.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009-2010 iWave Systems
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <console/console.h>
  17 #include <device/device.h>
  18 #include <device/pci.h>
  19 #include <device/pci_ids.h>
  20
  21 /* PCI Configuration Space (D31:F1): IDE */
  22 #define INTR_LN                 0x3c
  23 #define IDE_TIM_PRI             0x80    /* IDE timings, primary */
  24
  25 extern int sch_port_access_read(int port, int reg, int bytes);
  26
  27 static void ide_init(struct device *dev)
  28 {
  29         u32 ideTimingConfig, reg32;
  30
  31         printk(BIOS_DEBUG, "sch_ide: initializing... ");
  32
  33         reg32 = pci_read_config32(dev, PCI_COMMAND);
  34         pci_write_config32(dev, PCI_COMMAND,
  35                            reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
  36
  37         /* Program the clock. */
  38         if (sch_port_access_read(5, 3, 4) & (1 << 3)) {
  39                 /* 533MHz, Read PCI MC register */
  40                 reg32 = pci_read_config32(dev, 0x60);
  41                 pci_write_config32(dev, 0x60, reg32 | 1);
  42         } else {
  43                 /* 400MHz */
  44                 reg32 = pci_read_config32(dev, 0x60);
  45                 reg32 &= ~1;
  46                 pci_write_config32(dev, 0x60, reg32);
  47         }
  48
  49         /* Enable primary IDE interface. 80=04 81=00 82=02 83=80 */
  50         ideTimingConfig = 0x80020000;
  51         printk(BIOS_DEBUG, "IDE0 ");
  52         pci_write_config32(dev, IDE_TIM_PRI, ideTimingConfig);
  53
  54         /* Set Interrupt Line. */
  55         /* Interrupt Pin is set by D31IP.PIP */
  56         printk(BIOS_DEBUG, "\n");
  57 }
  58
  59 static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
  60 {
  61         if (!vendor || !device) {
  62                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
  63                                    pci_read_config32(dev, PCI_VENDOR_ID));
  64         } else {
  65                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
  66                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
  67         }
  68 }
  69
  70 static struct pci_operations ide_pci_ops = {
  71         .set_subsystem = ide_set_subsystem,
  72 };
  73
  74 static struct device_operations ide_ops = {
  75         .read_resources         = pci_dev_read_resources,
  76         .set_resources          = pci_dev_set_resources,
  77         .enable_resources       = pci_dev_enable_resources,
  78         .init                   = ide_init,
  79         .scan_bus               = 0,
  80         .ops_pci                = &ide_pci_ops,
  81 };
  82
  83 static const struct pci_driver sch_ide __pci_driver = {
  84         .ops    = &ide_ops,
  85         .vendor = PCI_VENDOR_ID_INTEL,
  86         .device = 0x811A,
  87 };