src/southbridge/intel/lynxpoint/usb_ehci.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <console/console.h>
  18 #include <delay.h>
  19 #include <device/device.h>
  20 #include <device/pci.h>
  21 #include <device/pci_ids.h>
  22 #include <device/pci_ehci.h>
  23 #include <arch/io.h>
  24 #include "pch.h"
  25
  26 #ifdef __SMM__
  27
  28 void usb_ehci_disable(device_t dev)
  29 {
  30         u16 reg16;
  31         u32 reg32;
  32
  33         /* Set 0xDC[0]=1 */
  34         pci_or_config32(dev, 0xdc, (1 << 0));
  35
  36         /* Set D3Hot state and disable PME */
  37         reg16 = pci_read_config16(dev, EHCI_PWR_CTL_STS);
  38         reg16 &= ~(PWR_CTL_ENABLE_PME | PWR_CTL_SET_MASK);
  39         reg16 |= PWR_CTL_SET_D3;
  40         pci_write_config16(dev, EHCI_PWR_CTL_STS, reg16);
  41
  42         /* Clear memory and bus master */
  43         pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
  44         reg32 = pci_read_config32(dev, PCI_COMMAND);
  45         reg32 &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  46         pci_write_config32(dev, PCI_COMMAND, reg32);
  47
  48         /* Disable device */
  49         switch (dev) {
  50         case PCH_EHCI1_DEV:
  51                 RCBA32_OR(FD, PCH_DISABLE_EHCI1);
  52                 break;
  53         case PCH_EHCI2_DEV:
  54                 RCBA32_OR(FD, PCH_DISABLE_EHCI2);
  55                 break;
  56         }
  57 }
  58
  59 /* Handler for EHCI controller on entry to S3/S4/S5 */
  60 void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ)
  61 {
  62         u32 reg32;
  63         u8 *bar0_base;
  64         u16 pwr_state;
  65         u16 pci_cmd;
  66
  67         /* Check if the controller is disabled or not present */
  68         bar0_base = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
  69         if (bar0_base == 0 || bar0_base == (u8 *)0xffffffff)
  70                 return;
  71         pci_cmd = pci_read_config32(dev, PCI_COMMAND);
  72
  73         switch (slp_typ) {
  74         case SLP_TYP_S4:
  75         case SLP_TYP_S5:
  76                 /* Check if controller is in D3 power state */
  77                 pwr_state = pci_read_config16(dev, EHCI_PWR_CTL_STS);
  78                 if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) {
  79                         /* Put in D0 */
  80                         u32 new_state = pwr_state & ~PWR_CTL_SET_MASK;
  81                         new_state |= PWR_CTL_SET_D0;
  82                         pci_write_config16(dev, EHCI_PWR_CTL_STS, new_state);
  83
  84                         /* Make sure memory bar is set */
  85                         pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)bar0_base);
  86
  87                         /* Make sure memory space is enabled */
  88                         pci_write_config16(dev, PCI_COMMAND, pci_cmd |
  89                                    PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
  90                 }
  91
  92                 /*
  93                  * If Run/Stop (bit0) is clear in USB2.0_CMD:
  94                  * - Clear Async Schedule Enable (bit5) and
  95                  * - Clear Periodic Schedule Enable (bit4) and
  96                  * - Set Run/Stop (bit0)
  97                  */
  98                 reg32 = read32(bar0_base + EHCI_USB_CMD);
  99                 if (reg32 & EHCI_USB_CMD_RUN) {
 100                         reg32 &= ~(EHCI_USB_CMD_PSE | EHCI_USB_CMD_ASE);
 101                         reg32 |= EHCI_USB_CMD_RUN;
 102                         write32(bar0_base + EHCI_USB_CMD, reg32);
 103                 }
 104
 105                 /* Check for Port Enabled in PORTSC(0) (RMH) */
 106                 reg32 = read32(bar0_base + EHCI_PORTSC(0));
 107                 if (reg32 & EHCI_PORTSC_ENABLED) {
 108                         /* Set suspend bit in PORTSC if not already set */
 109                         if (!(reg32 & EHCI_PORTSC_SUSPEND)) {
 110                                 reg32 |= EHCI_PORTSC_SUSPEND;
 111                                 write32(bar0_base + EHCI_PORTSC(0), reg32);
 112                         }
 113
 114                         /* Delay 25ms !! */
 115                         udelay(25 * 1000);
 116
 117                         /* Clear Run/Stop bit */
 118                         reg32 = read32(bar0_base + EHCI_USB_CMD);
 119                         reg32 &= EHCI_USB_CMD_RUN;
 120                         write32(bar0_base + EHCI_USB_CMD, reg32);
 121                 }
 122
 123                 /* Restore state to D3 if that is what it was at the start */
 124                 if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) {
 125                         /* Restore pci command reg */
 126                         pci_write_config16(dev, PCI_COMMAND, pci_cmd);
 127
 128                         /* Enable D3 */
 129                         pci_write_config16(dev, EHCI_PWR_CTL_STS, pwr_state);
 130                 }
 131         }
 132 }
 133
 134 #else /* !__SMM__ */
 135
 136 static void usb_ehci_clock_gating(struct device *dev)
 137 {
 138         u32 reg32;
 139
 140         /* IOBP 0xE5004001[7:6] = 11b */
 141         pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6));
 142
 143         /* Dx:F0:DCh[5,2,1] = 111b
 144          * Dx:F0:DCh[0] = 1b when EHCI controller is disabled */
 145         reg32 = pci_read_config32(dev, 0xdc);
 146         reg32 |= (1 << 5) | (1 << 2) | (1 << 1);
 147         pci_write_config32(dev, 0xdc, reg32);
 148
 149         /* Dx:F0:78h[1:0] = 11b */
 150         reg32 = pci_read_config32(dev, 0x78);
 151         reg32 |= (1 << 1) | (1 << 0);
 152         pci_write_config32(dev, 0x78, reg32);
 153 }
 154
 155 static void usb_ehci_init(struct device *dev)
 156 {
 157         printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
 158
 159         usb_ehci_clock_gating(dev);
 160
 161         /* Disable Wake on Disconnect in RMH */
 162         RCBA32_OR(0x35b0, 0x00000022);
 163
 164         printk(BIOS_DEBUG, "done.\n");
 165 }
 166
 167 static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 168 {
 169         u8 access_cntl;
 170
 171         access_cntl = pci_read_config8(dev, 0x80);
 172
 173         /* Enable writes to protected registers. */
 174         pci_write_config8(dev, 0x80, access_cntl | 1);
 175
 176         if (!vendor || !device) {
 177                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 178                                 pci_read_config32(dev, PCI_VENDOR_ID));
 179         } else {
 180                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 181                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 182         }
 183
 184         /* Restore protection. */
 185         pci_write_config8(dev, 0x80, access_cntl);
 186 }
 187
 188 static struct pci_operations lops_pci = {
 189         .set_subsystem  = &usb_ehci_set_subsystem,
 190 };
 191
 192 static struct device_operations usb_ehci_ops = {
 193         .read_resources         = pci_ehci_read_resources,
 194         .set_resources          = pci_dev_set_resources,
 195         .enable_resources       = pci_dev_enable_resources,
 196         .init                   = usb_ehci_init,
 197         .scan_bus               = 0,
 198         .ops_pci                = &lops_pci,
 199 };
 200
 201 static const unsigned short pci_device_ids[] = { 0x9c26, 0x8c26, 0x8c2d, 0 };
 202
 203 static const struct pci_driver pch_usb_ehci __pci_driver = {
 204         .ops     = &usb_ehci_ops,
 205         .vendor  = PCI_VENDOR_ID_INTEL,
 206         .devices = pci_device_ids,
 207 };
 208
 209 #endif /* !__SMM__ */