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tree: drop last paragraph of GPL copyright header
[coreboot.git] / src / southbridge / intel / lynxpoint / sata.c
blobffeb8a2fe8f3605c8e7b988c825cd9ca72376007
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <arch/io.h>
18 #include <console/console.h>
19 #include <device/device.h>
20 #include <device/pci.h>
21 #include <device/pci_ids.h>
22 #include <delay.h>
23 #include "pch.h"
24
25 typedef struct southbridge_intel_lynxpoint_config config_t;
26
27 static inline u32 sir_read(struct device *dev, int idx)
28 {
29 pci_write_config32(dev, SATA_SIRI, idx);
30 return pci_read_config32(dev, SATA_SIRD);
31 }
32
33 static inline void sir_write(struct device *dev, int idx, u32 value)
34 {
35 pci_write_config32(dev, SATA_SIRI, idx);
36 pci_write_config32(dev, SATA_SIRD, value);
37 }
38
39 static void sata_init(struct device *dev)
40 {
41 u32 reg32;
42 u16 reg16;
43 /* Get the chip configuration */
44 config_t *config = dev->chip_info;
45
46 printk(BIOS_DEBUG, "SATA: Initializing...\n");
47
48 if (config == NULL) {
49 printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n");
50 return;
51 }
52
53 /* SATA configuration */
54
55 /* Enable BARs */
56 pci_write_config16(dev, PCI_COMMAND, 0x0007);
57
58 if (config->ide_legacy_combined) {
59 printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");
60
61 /* No AHCI: clear AHCI base */
62 pci_write_config32(dev, 0x24, 0x00000000);
63 /* And without AHCI BAR no memory decoding */
64 reg16 = pci_read_config16(dev, PCI_COMMAND);
65 reg16 &= ~PCI_COMMAND_MEMORY;
66 pci_write_config16(dev, PCI_COMMAND, reg16);
67
68 pci_write_config8(dev, 0x09, 0x80);
69
70 /* Set timings */
71 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
72 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
73 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
74 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
75 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
76
77 /* Sync DMA */
78 pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
79 pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
80
81 /* Set IDE I/O Configuration */
82 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
83 pci_write_config32(dev, IDE_CONFIG, reg32);
84
85 /* Port enable */
86 reg16 = pci_read_config16(dev, 0x92);
87 reg16 &= ~0x3f;
88 reg16 |= config->sata_port_map;
89 pci_write_config16(dev, 0x92, reg16);
90
91 /* SATA Initialization register */
92 pci_write_config32(dev, 0x94,
93 ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
94 } else if(config->sata_ahci) {
95 u32 *abar;
96
97 printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
98
99 /* Set Interrupt Line */
100 /* Interrupt Pin is set by D31IP.PIP */
101 pci_write_config8(dev, INTR_LN, 0x0a);
102
103 /* Set timings */
104 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
105 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
106 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
107 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
108 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
109
110 /* Sync DMA */
111 pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
112 pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
113
114 /* Set IDE I/O Configuration */
115 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
116 pci_write_config32(dev, IDE_CONFIG, reg32);
117
118 /* for AHCI, Port Enable is managed in memory mapped space */
119 reg16 = pci_read_config16(dev, 0x92);
120 reg16 &= ~0x3f;
121 reg16 |= 0x8000 | config->sata_port_map;
122 pci_write_config16(dev, 0x92, reg16);
123 udelay(2);
124
125 /* Setup register 98h */
126 reg32 = pci_read_config16(dev, 0x98);
127 reg32 |= 1 << 19; /* BWG step 6 */
128 reg32 |= 1 << 22; /* BWG step 5 */
129 reg32 &= ~(0x3f << 7);
130 reg32 |= 0x04 << 7; /* BWG step 7 */
131 reg32 |= 1 << 20; /* BWG step 8 */
132 reg32 &= ~(0x03 << 5);
133 reg32 |= 1 << 5; /* BWG step 9 */
134 reg32 |= 1 << 18; /* BWG step 10 */
135 reg32 |= 1 << 29; /* BWG step 11 */
136 if (pch_is_lp()) {
137 reg32 &= ~((1 << 31) | (1 << 30));
138 reg32 |= 1 << 23;
139 reg32 |= 1 << 24; /* Disable listen mode (hotplug) */
140 }
141 pci_write_config32(dev, 0x98, reg32);
142
143 /* Setup register 9Ch */
144 reg16 = 0; /* Disable alternate ID */
145 reg16 = 1 << 5; /* BWG step 12 */
146 pci_write_config16(dev, 0x9c, reg16);
147
148 /* SATA Initialization register */
149 reg32 = 0x183;
150 reg32 |= (config->sata_port_map ^ 0x3f) << 24;
151 reg32 |= (config->sata_devslp_mux & 1) << 15;
152 pci_write_config32(dev, 0x94, reg32);
153
154 /* Initialize AHCI memory-mapped space */
155 abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
156 printk(BIOS_DEBUG, "ABAR: %p\n", abar);
157 /* CAP (HBA Capabilities) : enable power management */
158 reg32 = read32(abar + 0x00);
159 reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
160 reg32 &= ~0x00020060; // clear SXS+EMS+PMS
161 if (pch_is_lp())
162 reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY
163 write32(abar + 0x00, reg32);
164 /* PI (Ports implemented) */
165 write32(abar + 0x03, config->sata_port_map);
166 (void) read32(abar + 0x03); /* Read back 1 */
167 (void) read32(abar + 0x03); /* Read back 2 */
168 /* CAP2 (HBA Capabilities Extended)*/
169 reg32 = read32(abar + 0x09);
170 /* Enable DEVSLP */
171 if (pch_is_lp()) {
172 if (config->sata_devslp_disable)
173 reg32 &= ~(1 << 3);
174 else
175 reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2);
176 } else {
177 reg32 &= ~0x00000002;
178 }
179 write32(abar + 0x09, reg32);
180 } else {
181 printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
182
183 /* No AHCI: clear AHCI base */
184 pci_write_config32(dev, 0x24, 0x00000000);
185
186 /* And without AHCI BAR no memory decoding */
187 reg16 = pci_read_config16(dev, PCI_COMMAND);
188 reg16 &= ~PCI_COMMAND_MEMORY;
189 pci_write_config16(dev, PCI_COMMAND, reg16);
190
191 /* Native mode capable on both primary and secondary (0xa)
192 * or'ed with enabled (0x50) = 0xf
193 */
194 pci_write_config8(dev, 0x09, 0x8f);
195
196 /* Set Interrupt Line */
197 /* Interrupt Pin is set by D31IP.PIP */
198 pci_write_config8(dev, INTR_LN, 0xff);
199
200 /* Set timings */
201 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
202 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
203 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
204 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
205 IDE_SITRE | IDE_ISP_3_CLOCKS |
206 IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
207
208 /* Sync DMA */
209 pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
210 pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
211
212 /* Set IDE I/O Configuration */
213 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
214 pci_write_config32(dev, IDE_CONFIG, reg32);
215
216 /* Port enable */
217 reg16 = pci_read_config16(dev, 0x92);
218 reg16 &= ~0x3f;
219 reg16 |= config->sata_port_map;
220 pci_write_config16(dev, 0x92, reg16);
221
222 /* SATA Initialization register */
223 pci_write_config32(dev, 0x94,
224 ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
225 }
226
227 /* Set Gen3 Transmitter settings if needed */
228 if (config->sata_port0_gen3_tx)
229 pch_iobp_update(SATA_IOBP_SP0G3IR, 0,
230 config->sata_port0_gen3_tx);
231
232 if (config->sata_port1_gen3_tx)
233 pch_iobp_update(SATA_IOBP_SP1G3IR, 0,
234 config->sata_port1_gen3_tx);
235
236 /* Set Gen3 DTLE DATA / EDGE registers if needed */
237 if (config->sata_port0_gen3_dtle) {
238 pch_iobp_update(SATA_IOBP_SP0DTLE_DATA,
239 ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
240 (config->sata_port0_gen3_dtle & SATA_DTLE_MASK)
241 << SATA_DTLE_DATA_SHIFT);
242
243 pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE,
244 ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
245 (config->sata_port0_gen3_dtle & SATA_DTLE_MASK)
246 << SATA_DTLE_EDGE_SHIFT);
247 }
248
249 if (config->sata_port1_gen3_dtle) {
250 pch_iobp_update(SATA_IOBP_SP1DTLE_DATA,
251 ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
252 (config->sata_port1_gen3_dtle & SATA_DTLE_MASK)
253 << SATA_DTLE_DATA_SHIFT);
254
255 pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE,
256 ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
257 (config->sata_port1_gen3_dtle & SATA_DTLE_MASK)
258 << SATA_DTLE_EDGE_SHIFT);
259 }
260
261 /* Additional Programming Requirements */
262 /* Power Optimizer */
263
264 /* Step 1 */
265 if (pch_is_lp())
266 sir_write(dev, 0x64, 0x883c9003);
267 else
268 sir_write(dev, 0x64, 0x883c9001);
269
270 /* Step 2: SIR 68h[15:0] = 880Ah */
271 reg32 = sir_read(dev, 0x68);
272 reg32 &= 0xffff0000;
273 reg32 |= 0x880a;
274 sir_write(dev, 0x68, reg32);
275
276 /* Step 3: SIR 60h[3] = 1 */
277 reg32 = sir_read(dev, 0x60);
278 reg32 |= (1 << 3);
279 sir_write(dev, 0x60, reg32);
280
281 /* Step 4: SIR 60h[0] = 1 */
282 reg32 = sir_read(dev, 0x60);
283 reg32 |= (1 << 0);
284 sir_write(dev, 0x60, reg32);
285
286 /* Step 5: SIR 60h[1] = 1 */
287 reg32 = sir_read(dev, 0x60);
288 reg32 |= (1 << 1);
289 sir_write(dev, 0x60, reg32);
290
291 /* Clock Gating */
292 sir_write(dev, 0x70, 0x3f00bf1f);
293 if (pch_is_lp()) {
294 sir_write(dev, 0x54, 0xcf000f0f);
295 sir_write(dev, 0x58, 0x00190000);
296 }
297
298 reg32 = pci_read_config32(dev, 0x300);
299 reg32 |= (1 << 17) | (1 << 16);
300 reg32 |= (1 << 31) | (1 << 30) | (1 << 29);
301 pci_write_config32(dev, 0x300, reg32);
302 }
303
304 static void sata_enable(device_t dev)
305 {
306 /* Get the chip configuration */
307 config_t *config = dev->chip_info;
308 u16 map = 0;
309
310 if (!config)
311 return;
312
313 /*
314 * Set SATA controller mode early so the resource allocator can
315 * properly assign IO/Memory resources for the controller.
316 */
317 if (config->sata_ahci)
318 map = 0x0060;
319
320 map |= (config->sata_port_map ^ 0x3f) << 8;
321
322 pci_write_config16(dev, 0x90, map);
323 }
324
325 static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
326 {
327 if (!vendor || !device) {
328 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
329 pci_read_config32(dev, PCI_VENDOR_ID));
330 } else {
331 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
332 ((device & 0xffff) << 16) | (vendor & 0xffff));
333 }
334 }
335
336 static struct pci_operations sata_pci_ops = {
337 .set_subsystem = sata_set_subsystem,
338 };
339
340 static struct device_operations sata_ops = {
341 .read_resources = pci_dev_read_resources,
342 .set_resources = pci_dev_set_resources,
343 .enable_resources = pci_dev_enable_resources,
344 .init = sata_init,
345 .enable = sata_enable,
346 .scan_bus = 0,
347 .ops_pci = &sata_pci_ops,
348 };
349
350 static const unsigned short pci_device_ids[] = {
351 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, /* Desktop */
352 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, /* Mobile */
353 0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* Low Power */
354 0
355 };
356
357 static const struct pci_driver pch_sata __pci_driver = {
358 .ops = &sata_ops,
359 .vendor = PCI_VENDOR_ID_INTEL,
360 .devices = pci_device_ids,
361 };
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