src/southbridge/intel/lynxpoint/finalize.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <arch/io.h>
  18 #include <console/post_codes.h>
  19 #include <spi-generic.h>
  20 #include "me.h"
  21 #include "pch.h"
  22
  23 void intel_pch_finalize_smm(void)
  24 {
  25         /* Lock down Management Engine */
  26         intel_me_finalize_smm();
  27
  28         /* Set SPI opcode menu */
  29         RCBA16(0x3894) = SPI_OPPREFIX;
  30         RCBA16(0x3896) = SPI_OPTYPE;
  31         RCBA32(0x3898) = SPI_OPMENU_LOWER;
  32         RCBA32(0x389c) = SPI_OPMENU_UPPER;
  33
  34         /* Lock SPIBAR */
  35         RCBA32_OR(0x3804, (1 << 15));
  36
  37 #if CONFIG_SPI_FLASH_SMM
  38         /* Re-init SPI driver to handle locked BAR */
  39         spi_init();
  40 #endif
  41
  42         /* TCLOCKDN: TC Lockdown */
  43         RCBA32_OR(0x0050, (1 << 31));
  44
  45         /* BIOS Interface Lockdown */
  46         RCBA32_OR(0x3410, (1 << 0));
  47
  48         /* Function Disable SUS Well Lockdown */
  49         RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
  50
  51         /* Global SMI Lock */
  52         pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
  53
  54         /* GEN_PMCON Lock */
  55         pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
  56
  57         /* PMSYNC */
  58         RCBA32_OR(PMSYNC_CONFIG, (1 << 31));
  59
  60         /* R/WO registers */
  61         RCBA32(0x21a4) = RCBA32(0x21a4);
  62         pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
  63                     pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
  64
  65         /* Indicate finalize step with post code */
  66         outb(POST_OS_BOOT, 0x80);
  67 }