?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
tree: drop last paragraph of GPL copyright header
[coreboot.git] / src / southbridge / intel / ibexpeak / smihandler.c
blob04ef75d238ca778a74f13fef6ac72a623716e268
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <types.h>
18 #include <arch/io.h>
19 #include <console/console.h>
20 #include <cpu/x86/cache.h>
21 #include <device/pci_def.h>
22 #include <cpu/x86/smm.h>
23 #include <elog.h>
24 #include <halt.h>
25 #include <pc80/mc146818rtc.h>
26 #include "pch.h"
27
28 #include "nvs.h"
29
30 /* We are using PCIe accesses for now
31 * 1. the chipset can do it
32 * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
33 */
34 #include "northbridge/intel/nehalem/nehalem.h"
35 #include <arch/pci_mmio_cfg.h>
36
37 /* While we read PMBASE dynamically in case it changed, let's
38 * initialize it with a sane value
39 */
40 static u16 pmbase = DEFAULT_PMBASE;
41 u16 smm_get_pmbase(void)
42 {
43 return pmbase;
44 }
45
46 static u8 smm_initialized = 0;
47
48 /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
49 * by coreboot.
50 */
51 static global_nvs_t *gnvs;
52 global_nvs_t *smm_get_gnvs(void)
53 {
54 return gnvs;
55 }
56
57 static void alt_gpi_mask(u16 clr, u16 set)
58 {
59 u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN);
60 alt_gp &= ~clr;
61 alt_gp |= set;
62 outw(alt_gp, pmbase + ALT_GP_SMI_EN);
63 }
64
65 static void gpe0_mask(u32 clr, u32 set)
66 {
67 u32 gpe0 = inl(pmbase + GPE0_EN);
68 gpe0 &= ~clr;
69 gpe0 |= set;
70 outl(gpe0, pmbase + GPE0_EN);
71 }
72
73 void gpi_route_interrupt(u8 gpi, u8 mode)
74 {
75 u32 gpi_rout;
76 if (gpi >= 16)
77 return;
78
79 alt_gpi_mask(1 << gpi, 0);
80 gpe0_mask(1 << (gpi+16), 0);
81
82 gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
83 gpi_rout &= ~(3 << (2 * gpi));
84 gpi_rout |= ((mode & 3) << (2 * gpi));
85 pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout);
86
87 if (mode == GPI_IS_SCI)
88 gpe0_mask(0, 1 << (gpi+16));
89 else if (mode == GPI_IS_SMI)
90 alt_gpi_mask(0, 1 << gpi);
91 }
92
93 /**
94 * @brief read and clear PM1_STS
95 * @return PM1_STS register
96 */
97 static u16 reset_pm1_status(void)
98 {
99 u16 reg16;
100
101 reg16 = inw(pmbase + PM1_STS);
102 /* set status bits are cleared by writing 1 to them */
103 outw(reg16, pmbase + PM1_STS);
104
105 return reg16;
106 }
107
108 static void dump_pm1_status(u16 pm1_sts)
109 {
110 printk(BIOS_SPEW, "PM1_STS: ");
111 if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
112 if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
113 if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
114 if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
115 if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN ");
116 if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL ");
117 if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM ");
118 if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF ");
119 printk(BIOS_SPEW, "\n");
120 int reg16 = inw(pmbase + PM1_EN);
121 printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
122 }
123
124 /**
125 * @brief read and clear SMI_STS
126 * @return SMI_STS register
127 */
128 static u32 reset_smi_status(void)
129 {
130 u32 reg32;
131
132 reg32 = inl(pmbase + SMI_STS);
133 /* set status bits are cleared by writing 1 to them */
134 outl(reg32, pmbase + SMI_STS);
135
136 return reg32;
137 }
138
139 static void dump_smi_status(u32 smi_sts)
140 {
141 printk(BIOS_DEBUG, "SMI_STS: ");
142 if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
143 if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
144 if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
145 if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
146 if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
147 if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
148 if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
149 if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
150 if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
151 if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
152 if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
153 if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
154 if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
155 if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
156 if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
157 if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
158 if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
159 if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
160 if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
161 printk(BIOS_DEBUG, "\n");
162 }
163
164
165 /**
166 * @brief read and clear GPE0_STS
167 * @return GPE0_STS register
168 */
169 static u32 reset_gpe0_status(void)
170 {
171 u32 reg32;
172
173 reg32 = inl(pmbase + GPE0_STS);
174 /* set status bits are cleared by writing 1 to them */
175 outl(reg32, pmbase + GPE0_STS);
176
177 return reg32;
178 }
179
180 static void dump_gpe0_status(u32 gpe0_sts)
181 {
182 int i;
183 printk(BIOS_DEBUG, "GPE0_STS: ");
184 for (i=31; i>= 16; i--) {
185 if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
186 }
187 if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
188 if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
189 if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
190 if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
191 if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "BATLOW ");
192 if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
193 if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
194 if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
195 if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
196 if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
197 if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
198 if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
199 if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE ");
200 if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOTPLUG ");
201 if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
202 printk(BIOS_DEBUG, "\n");
203 }
204
205
206 /**
207 * @brief read and clear TCOx_STS
208 * @return TCOx_STS registers
209 */
210 static u32 reset_tco_status(void)
211 {
212 u32 tcobase = pmbase + 0x60;
213 u32 reg32;
214
215 reg32 = inl(tcobase + 0x04);
216 /* set status bits are cleared by writing 1 to them */
217 outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
218 if (reg32 & (1 << 18))
219 outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
220
221 return reg32;
222 }
223
224
225 static void dump_tco_status(u32 tco_sts)
226 {
227 printk(BIOS_DEBUG, "TCO_STS: ");
228 if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
229 if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
230 if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
231 if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
232 if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
233 if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
234 if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
235 if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
236 if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
237 if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
238 if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
239 if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
240 if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
241 printk(BIOS_DEBUG, "\n");
242 }
243
244 int southbridge_io_trap_handler(int smif)
245 {
246 switch (smif) {
247 case 0x32:
248 printk(BIOS_DEBUG, "OS Init\n");
249 /* gnvs->smif:
250 * On success, the IO Trap Handler returns 0
251 * On failure, the IO Trap Handler returns a value != 0
252 */
253 gnvs->smif = 0;
254 return 1; /* IO trap handled */
255 }
256
257 /* Not handled */
258 return 0;
259 }
260
261 /**
262 * @brief Set the EOS bit
263 */
264 void southbridge_smi_set_eos(void)
265 {
266 u8 reg8;
267
268 reg8 = inb(pmbase + SMI_EN);
269 reg8 |= EOS;
270 outb(reg8, pmbase + SMI_EN);
271 }
272
273 static void busmaster_disable_on_bus(int bus)
274 {
275 int slot, func;
276 unsigned int val;
277 unsigned char hdr;
278
279 for (slot = 0; slot < 0x20; slot++) {
280 for (func = 0; func < 8; func++) {
281 u32 reg32;
282 device_t dev = PCI_DEV(bus, slot, func);
283
284 val = pci_read_config32(dev, PCI_VENDOR_ID);
285
286 if (val == 0xffffffff || val == 0x00000000 ||
287 val == 0x0000ffff || val == 0xffff0000)
288 continue;
289
290 /* Disable Bus Mastering for this one device */
291 reg32 = pci_read_config32(dev, PCI_COMMAND);
292 reg32 &= ~PCI_COMMAND_MASTER;
293 pci_write_config32(dev, PCI_COMMAND, reg32);
294
295 /* If this is a bridge, then follow it. */
296 hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
297 hdr &= 0x7f;
298 if (hdr == PCI_HEADER_TYPE_BRIDGE ||
299 hdr == PCI_HEADER_TYPE_CARDBUS) {
300 unsigned int buses;
301 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
302 busmaster_disable_on_bus((buses >> 8) & 0xff);
303 }
304 }
305 }
306 }
307
308 static void southbridge_gate_memory_reset_real(int offset,
309 u16 use, u16 io, u16 lvl)
310 {
311 u32 reg32;
312
313 /* Make sure it is set as GPIO */
314 reg32 = inl(use);
315 if (!(reg32 & (1 << offset))) {
316 reg32 |= (1 << offset);
317 outl(reg32, use);
318 }
319
320 /* Make sure it is set as output */
321 reg32 = inl(io);
322 if (reg32 & (1 << offset)) {
323 reg32 &= ~(1 << offset);
324 outl(reg32, io);
325 }
326
327 /* Drive the output low */
328 reg32 = inl(lvl);
329 reg32 &= ~(1 << offset);
330 outl(reg32, lvl);
331 }
332
333 /*
334 * Drive GPIO 60 low to gate memory reset in S3.
335 *
336 * Intel reference designs all use GPIO 60 but it is
337 * not a requirement and boards could use a different pin.
338 */
339 static void southbridge_gate_memory_reset(void)
340 {
341 u16 gpiobase;
342
343 gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
344 if (!gpiobase)
345 return;
346
347 if (CONFIG_DRAM_RESET_GATE_GPIO >= 32)
348 southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO - 32,
349 gpiobase + GPIO_USE_SEL2,
350 gpiobase + GP_IO_SEL2,
351 gpiobase + GP_LVL2);
352 else
353 southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO,
354 gpiobase + GPIO_USE_SEL,
355 gpiobase + GP_IO_SEL,
356 gpiobase + GP_LVL);
357 }
358
359 static void xhci_sleep(u8 slp_typ)
360 {
361 u32 reg32, xhci_bar;
362 u16 reg16;
363
364 switch (slp_typ) {
365 case SLP_TYP_S3:
366 case SLP_TYP_S4:
367 reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);
368 reg16 &= ~0x03UL;
369 pci_write_config32(PCH_XHCI_DEV, 0x74, reg16);
370
371 reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND);
372 reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
373 pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32);
374
375 xhci_bar = pci_read_config32(PCH_XHCI_DEV,
376 PCI_BASE_ADDRESS_0) & ~0xFUL;
377
378 if ((xhci_bar + 0x4C0) & 1)
379 pch_iobp_update(0xEC000082, ~0UL, (3 << 2));
380 if ((xhci_bar + 0x4D0) & 1)
381 pch_iobp_update(0xEC000182, ~0UL, (3 << 2));
382 if ((xhci_bar + 0x4E0) & 1)
383 pch_iobp_update(0xEC000282, ~0UL, (3 << 2));
384 if ((xhci_bar + 0x4F0) & 1)
385 pch_iobp_update(0xEC000382, ~0UL, (3 << 2));
386
387 reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND);
388 reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
389 pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32);
390
391 reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);
392 reg16 |= 0x03;
393 pci_write_config16(PCH_XHCI_DEV, 0x74, reg16);
394 break;
395
396 case SLP_TYP_S5:
397 reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);
398 reg16 |= ((1 << 8) | 0x03);
399 pci_write_config16(PCH_XHCI_DEV, 0x74, reg16);
400 break;
401 }
402 }
403
404
405 static void southbridge_smi_sleep(void)
406 {
407 u8 reg8;
408 u32 reg32;
409 u8 slp_typ;
410 u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
411
412 // save and recover RTC port values
413 u8 tmp70, tmp72;
414 tmp70 = inb(0x70);
415 tmp72 = inb(0x72);
416 get_option(&s5pwr, "power_on_after_fail");
417 outb(tmp70, 0x70);
418 outb(tmp72, 0x72);
419
420 /* First, disable further SMIs */
421 reg8 = inb(pmbase + SMI_EN);
422 reg8 &= ~SLP_SMI_EN;
423 outb(reg8, pmbase + SMI_EN);
424
425 /* Figure out SLP_TYP */
426 reg32 = inl(pmbase + PM1_CNT);
427 printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
428 slp_typ = (reg32 >> 10) & 7;
429
430 if (smm_get_gnvs()->xhci)
431 xhci_sleep(slp_typ);
432
433 /* Do any mainboard sleep handling */
434 mainboard_smi_sleep(slp_typ-2);
435
436 #if CONFIG_ELOG_GSMI
437 /* Log S3, S4, and S5 entry */
438 if (slp_typ >= 5)
439 elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2);
440 #endif
441
442 /* Next, do the deed.
443 */
444
445 switch (slp_typ) {
446 case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
447 case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
448 case 5:
449 printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
450
451 /* Gate memory reset */
452 southbridge_gate_memory_reset();
453
454 /* Invalidate the cache before going to S3 */
455 wbinvd();
456 break;
457 case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
458 case 7:
459 printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
460
461 outl(0, pmbase + GPE0_EN);
462
463 /* Always set the flag in case CMOS was changed on runtime. For
464 * "KEEP", switch to "OFF" - KEEP is software emulated
465 */
466 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
467 if (s5pwr == MAINBOARD_POWER_ON) {
468 reg8 &= ~1;
469 } else {
470 reg8 |= 1;
471 }
472 pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
473
474 /* also iterates over all bridges on bus 0 */
475 busmaster_disable_on_bus(0);
476 break;
477 default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
478 }
479
480 /* Write back to the SLP register to cause the originally intended
481 * event again. We need to set BIT13 (SLP_EN) though to make the
482 * sleep happen.
483 */
484 outl(reg32 | SLP_EN, pmbase + PM1_CNT);
485
486 /* Make sure to stop executing code here for S3/S4/S5 */
487 if (slp_typ > 1)
488 halt();
489
490 /* In most sleep states, the code flow of this function ends at
491 * the line above. However, if we entered sleep state S1 and wake
492 * up again, we will continue to execute code in this function.
493 */
494 reg32 = inl(pmbase + PM1_CNT);
495 if (reg32 & SCI_EN) {
496 /* The OS is not an ACPI OS, so we set the state to S0 */
497 reg32 &= ~(SLP_EN | SLP_TYP);
498 outl(reg32, pmbase + PM1_CNT);
499 }
500 }
501
502 /*
503 * Look for Synchronous IO SMI and use save state from that
504 * core in case we are not running on the same core that
505 * initiated the IO transaction.
506 */
507 static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
508 {
509 em64t101_smm_state_save_area_t *state;
510 int node;
511
512 /* Check all nodes looking for the one that issued the IO */
513 for (node = 0; node < CONFIG_MAX_CPUS; node++) {
514 state = smm_get_save_state(node);
515
516 /* Check for Synchronous IO (bit0==1) */
517 if (!(state->io_misc_info & (1 << 0)))
518 continue;
519
520 /* Make sure it was a write (bit4==0) */
521 if (state->io_misc_info & (1 << 4))
522 continue;
523
524 /* Check for APMC IO port */
525 if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)
526 continue;
527
528 /* Check AX against the requested command */
529 if ((state->rax & 0xff) != cmd)
530 continue;
531
532 return state;
533 }
534
535 return NULL;
536 }
537
538 #if CONFIG_ELOG_GSMI
539 static void southbridge_smi_gsmi(void)
540 {
541 u32 *ret, *param;
542 u8 sub_command;
543 em64t101_smm_state_save_area_t *io_smi =
544 smi_apmc_find_state_save(ELOG_GSMI_APM_CNT);
545
546 if (!io_smi)
547 return;
548
549 /* Command and return value in EAX */
550 ret = (u32*)&io_smi->rax;
551 sub_command = (u8)(*ret >> 8);
552
553 /* Parameter buffer in EBX */
554 param = (u32*)&io_smi->rbx;
555
556 /* drivers/elog/gsmi.c */
557 *ret = gsmi_exec(sub_command, param);
558 }
559 #endif
560
561 static void southbridge_smi_apmc(void)
562 {
563 u32 pmctrl;
564 u8 reg8;
565 em64t101_smm_state_save_area_t *state;
566
567 /* Emulate B2 register as the FADT / Linux expects it */
568
569 reg8 = inb(APM_CNT);
570 switch (reg8) {
571 case APM_CNT_CST_CONTROL:
572 /* Calling this function seems to cause
573 * some kind of race condition in Linux
574 * and causes a kernel oops
575 */
576 printk(BIOS_DEBUG, "C-state control\n");
577 break;
578 case APM_CNT_PST_CONTROL:
579 /* Calling this function seems to cause
580 * some kind of race condition in Linux
581 * and causes a kernel oops
582 */
583 printk(BIOS_DEBUG, "P-state control\n");
584 break;
585 case APM_CNT_ACPI_DISABLE:
586 pmctrl = inl(pmbase + PM1_CNT);
587 pmctrl &= ~SCI_EN;
588 outl(pmctrl, pmbase + PM1_CNT);
589 printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
590 break;
591 case APM_CNT_ACPI_ENABLE:
592 pmctrl = inl(pmbase + PM1_CNT);
593 pmctrl |= SCI_EN;
594 outl(pmctrl, pmbase + PM1_CNT);
595 printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
596 break;
597 case APM_CNT_GNVS_UPDATE:
598 if (smm_initialized) {
599 printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
600 return;
601 }
602 state = smi_apmc_find_state_save(reg8);
603 if (state) {
604 /* EBX in the state save contains the GNVS pointer */
605 gnvs = (global_nvs_t *)((u32)state->rbx);
606 smm_initialized = 1;
607 printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
608 }
609 break;
610 #if CONFIG_ELOG_GSMI
611 case ELOG_GSMI_APM_CNT:
612 southbridge_smi_gsmi();
613 break;
614 #endif
615 }
616
617 mainboard_smi_apmc(reg8);
618 }
619
620 static void southbridge_smi_pm1(void)
621 {
622 u16 pm1_sts;
623
624 pm1_sts = reset_pm1_status();
625 dump_pm1_status(pm1_sts);
626
627 /* While OSPM is not active, poweroff immediately
628 * on a power button event.
629 */
630 if (pm1_sts & PWRBTN_STS) {
631 // power button pressed
632 u32 reg32;
633 reg32 = (7 << 10) | (1 << 13);
634 #if CONFIG_ELOG_GSMI
635 elog_add_event(ELOG_TYPE_POWER_BUTTON);
636 #endif
637 outl(reg32, pmbase + PM1_CNT);
638 }
639 }
640
641 static void southbridge_smi_gpe0(void)
642 {
643 u32 gpe0_sts;
644
645 gpe0_sts = reset_gpe0_status();
646 dump_gpe0_status(gpe0_sts);
647 }
648
649 static void southbridge_smi_gpi(void)
650 {
651 u16 reg16;
652 reg16 = inw(pmbase + ALT_GP_SMI_STS);
653 outw(reg16, pmbase + ALT_GP_SMI_STS);
654
655 reg16 &= inw(pmbase + ALT_GP_SMI_EN);
656
657 mainboard_smi_gpi(reg16);
658
659 if (reg16)
660 printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
661
662 outw(reg16, pmbase + ALT_GP_SMI_STS);
663 }
664
665 static void southbridge_smi_mc(void)
666 {
667 u32 reg32;
668
669 reg32 = inl(pmbase + SMI_EN);
670
671 /* Are periodic SMIs enabled? */
672 if ((reg32 & MCSMI_EN) == 0)
673 return;
674
675 printk(BIOS_DEBUG, "Microcontroller SMI.\n");
676 }
677
678
679
680 static void southbridge_smi_tco(void)
681 {
682 u32 tco_sts;
683
684 tco_sts = reset_tco_status();
685
686 /* Any TCO event? */
687 if (!tco_sts)
688 return;
689
690 if (tco_sts & (1 << 8)) { // BIOSWR
691 u8 bios_cntl;
692
693 bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
694
695 if (bios_cntl & 1) {
696 /* BWE is RW, so the SMI was caused by a
697 * write to BWE, not by a write to the BIOS
698 */
699
700 /* This is the place where we notice someone
701 * is trying to tinker with the BIOS. We are
702 * trying to be nice and just ignore it. A more
703 * resolute answer would be to power down the
704 * box.
705 */
706 printk(BIOS_DEBUG, "Switching back to RO\n");
707 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
708 } /* No else for now? */
709 } else if (tco_sts & (1 << 3)) { /* TIMEOUT */
710 /* Handle TCO timeout */
711 printk(BIOS_DEBUG, "TCO Timeout.\n");
712 } else if (!tco_sts) {
713 dump_tco_status(tco_sts);
714 }
715 }
716
717 static void southbridge_smi_periodic(void)
718 {
719 u32 reg32;
720
721 reg32 = inl(pmbase + SMI_EN);
722
723 /* Are periodic SMIs enabled? */
724 if ((reg32 & PERIODIC_EN) == 0)
725 return;
726
727 printk(BIOS_DEBUG, "Periodic SMI.\n");
728 }
729
730 static void southbridge_smi_monitor(void)
731 {
732 #define IOTRAP(x) (trap_sts & (1 << x))
733 u32 trap_sts, trap_cycle;
734 u32 data, mask = 0;
735 int i;
736
737 trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
738 RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
739
740 trap_cycle = RCBA32(0x1e10);
741 for (i=16; i<20; i++) {
742 if (trap_cycle & (1 << i))
743 mask |= (0xff << ((i - 16) << 2));
744 }
745
746
747 /* IOTRAP(3) SMI function call */
748 if (IOTRAP(3)) {
749 if (gnvs && gnvs->smif)
750 io_trap_handler(gnvs->smif); // call function smif
751 return;
752 }
753
754 /* IOTRAP(2) currently unused
755 * IOTRAP(1) currently unused */
756
757 /* IOTRAP(0) SMIC */
758 if (IOTRAP(0)) {
759 if (!(trap_cycle & (1 << 24))) { // It's a write
760 printk(BIOS_DEBUG, "SMI1 command\n");
761 data = RCBA32(0x1e18);
762 data &= mask;
763 // if (smi1)
764 // southbridge_smi_command(data);
765 // return;
766 }
767 // Fall through to debug
768 }
769
770 printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
771 for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
772 printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
773 printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
774 printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
775
776 if (!(trap_cycle & (1 << 24))) {
777 /* Write Cycle */
778 data = RCBA32(0x1e18);
779 printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);
780 }
781 #undef IOTRAP
782 }
783
784 typedef void (*smi_handler_t)(void);
785
786 static smi_handler_t southbridge_smi[32] = {
787 NULL, // [0] reserved
788 NULL, // [1] reserved
789 NULL, // [2] BIOS_STS
790 NULL, // [3] LEGACY_USB_STS
791 southbridge_smi_sleep, // [4] SLP_SMI_STS
792 southbridge_smi_apmc, // [5] APM_STS
793 NULL, // [6] SWSMI_TMR_STS
794 NULL, // [7] reserved
795 southbridge_smi_pm1, // [8] PM1_STS
796 southbridge_smi_gpe0, // [9] GPE0_STS
797 southbridge_smi_gpi, // [10] GPI_STS
798 southbridge_smi_mc, // [11] MCSMI_STS
799 NULL, // [12] DEVMON_STS
800 southbridge_smi_tco, // [13] TCO_STS
801 southbridge_smi_periodic, // [14] PERIODIC_STS
802 NULL, // [15] SERIRQ_SMI_STS
803 NULL, // [16] SMBUS_SMI_STS
804 NULL, // [17] LEGACY_USB2_STS
805 NULL, // [18] INTEL_USB2_STS
806 NULL, // [19] reserved
807 NULL, // [20] PCI_EXP_SMI_STS
808 southbridge_smi_monitor, // [21] MONITOR_STS
809 NULL, // [22] reserved
810 NULL, // [23] reserved
811 NULL, // [24] reserved
812 NULL, // [25] EL_SMI_STS
813 NULL, // [26] SPI_STS
814 NULL, // [27] reserved
815 NULL, // [28] reserved
816 NULL, // [29] reserved
817 NULL, // [30] reserved
818 NULL // [31] reserved
819 };
820
821 /**
822 * @brief Interrupt handler for SMI#
823 * @param node
824 * @param state_save
825 */
826 void southbridge_smi_handler(void)
827 {
828 int i, dump = 0;
829 u32 smi_sts;
830
831 /* Update global variable pmbase */
832 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
833
834 /* We need to clear the SMI status registers, or we won't see what's
835 * happening in the following calls.
836 */
837 smi_sts = reset_smi_status();
838
839 /* Call SMI sub handler for each of the status bits */
840 for (i = 0; i < 31; i++) {
841 if (smi_sts & (1 << i)) {
842 if (southbridge_smi[i]) {
843 southbridge_smi[i]();
844 } else {
845 printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
846 "handler available.\n", i);
847 dump = 1;
848 }
849 }
850 }
851
852 if(dump) {
853 dump_smi_status(smi_sts);
854 }
855
856 }
ast, secure and flexible OpenSource firmware