src/southbridge/intel/ibexpeak/smi.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #define __SIMPLE_DEVICE__
  18
  19 #include <device/device.h>
  20 #include <device/pci.h>
  21 #include <console/console.h>
  22 #include <arch/io.h>
  23 #include <cpu/cpu.h>
  24 #include <cpu/x86/cache.h>
  25 #include <cpu/x86/smm.h>
  26 #include <string.h>
  27 #include <cpu/intel/smm/gen1/smi.h>
  28 #include "pch.h"
  29
  30 /* While we read PMBASE dynamically in case it changed, let's
  31  * initialize it with a sane value
  32  */
  33 static u16 pmbase = DEFAULT_PMBASE;
  34
  35 /**
  36  * @brief read and clear PM1_STS
  37  * @return PM1_STS register
  38  */
  39 static u16 reset_pm1_status(void)
  40 {
  41         u16 reg16;
  42
  43         reg16 = inw(pmbase + PM1_STS);
  44         /* set status bits are cleared by writing 1 to them */
  45         outw(reg16, pmbase + PM1_STS);
  46
  47         return reg16;
  48 }
  49
  50 static void dump_pm1_status(u16 pm1_sts)
  51 {
  52         printk(BIOS_DEBUG, "PM1_STS: ");
  53         if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");
  54         if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");
  55         if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");
  56         if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");
  57         if (pm1_sts & (1 <<  8)) printk(BIOS_DEBUG, "PWRBTN ");
  58         if (pm1_sts & (1 <<  5)) printk(BIOS_DEBUG, "GBL ");
  59         if (pm1_sts & (1 <<  4)) printk(BIOS_DEBUG, "BM ");
  60         if (pm1_sts & (1 <<  0)) printk(BIOS_DEBUG, "TMROF ");
  61         printk(BIOS_DEBUG, "\n");
  62 }
  63
  64 /**
  65  * @brief read and clear SMI_STS
  66  * @return SMI_STS register
  67  */
  68 static u32 reset_smi_status(void)
  69 {
  70         u32 reg32;
  71
  72         reg32 = inl(pmbase + SMI_STS);
  73         /* set status bits are cleared by writing 1 to them */
  74         outl(reg32, pmbase + SMI_STS);
  75
  76         return reg32;
  77 }
  78
  79 static void dump_smi_status(u32 smi_sts)
  80 {
  81         printk(BIOS_DEBUG, "SMI_STS: ");
  82         if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
  83         if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
  84         if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
  85         if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
  86         if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
  87         if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
  88         if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
  89         if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
  90         if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
  91         if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
  92         if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
  93         if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
  94         if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
  95         if (smi_sts & (1 <<  9)) printk(BIOS_DEBUG, "GPE0 ");
  96         if (smi_sts & (1 <<  8)) printk(BIOS_DEBUG, "PM1 ");
  97         if (smi_sts & (1 <<  6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
  98         if (smi_sts & (1 <<  5)) printk(BIOS_DEBUG, "APM ");
  99         if (smi_sts & (1 <<  4)) printk(BIOS_DEBUG, "SLP_SMI ");
 100         if (smi_sts & (1 <<  3)) printk(BIOS_DEBUG, "LEGACY_USB ");
 101         if (smi_sts & (1 <<  2)) printk(BIOS_DEBUG, "BIOS ");
 102         printk(BIOS_DEBUG, "\n");
 103 }
 104
 105
 106 /**
 107  * @brief read and clear GPE0_STS
 108  * @return GPE0_STS register
 109  */
 110 static u32 reset_gpe0_status(void)
 111 {
 112         u32 reg32;
 113
 114         reg32 = inl(pmbase + GPE0_STS);
 115         /* set status bits are cleared by writing 1 to them */
 116         outl(reg32, pmbase + GPE0_STS);
 117
 118         return reg32;
 119 }
 120
 121 static void dump_gpe0_status(u32 gpe0_sts)
 122 {
 123         int i;
 124         printk(BIOS_DEBUG, "GPE0_STS: ");
 125         for (i=31; i>= 16; i--) {
 126                 if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
 127         }
 128         if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
 129         if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
 130         if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
 131         if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
 132         if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
 133         if (gpe0_sts & (1 <<  9)) printk(BIOS_DEBUG, "PCI_EXP ");
 134         if (gpe0_sts & (1 <<  8)) printk(BIOS_DEBUG, "RI ");
 135         if (gpe0_sts & (1 <<  7)) printk(BIOS_DEBUG, "SMB_WAK ");
 136         if (gpe0_sts & (1 <<  6)) printk(BIOS_DEBUG, "TCO_SCI ");
 137         if (gpe0_sts & (1 <<  5)) printk(BIOS_DEBUG, "AC97 ");
 138         if (gpe0_sts & (1 <<  4)) printk(BIOS_DEBUG, "USB2 ");
 139         if (gpe0_sts & (1 <<  3)) printk(BIOS_DEBUG, "USB1 ");
 140         if (gpe0_sts & (1 <<  2)) printk(BIOS_DEBUG, "HOT_PLUG ");
 141         if (gpe0_sts & (1 <<  0)) printk(BIOS_DEBUG, "THRM ");
 142         printk(BIOS_DEBUG, "\n");
 143 }
 144
 145
 146 /**
 147  * @brief read and clear ALT_GP_SMI_STS
 148  * @return ALT_GP_SMI_STS register
 149  */
 150 static u16 reset_alt_gp_smi_status(void)
 151 {
 152         u16 reg16;
 153
 154         reg16 = inl(pmbase + ALT_GP_SMI_STS);
 155         /* set status bits are cleared by writing 1 to them */
 156         outl(reg16, pmbase + ALT_GP_SMI_STS);
 157
 158         return reg16;
 159 }
 160
 161 static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
 162 {
 163         int i;
 164         printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");
 165         for (i=15; i>= 0; i--) {
 166                 if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i);
 167         }
 168         printk(BIOS_DEBUG, "\n");
 169 }
 170
 171
 172
 173 /**
 174  * @brief read and clear TCOx_STS
 175  * @return TCOx_STS registers
 176  */
 177 static u32 reset_tco_status(void)
 178 {
 179         u32 tcobase = pmbase + 0x60;
 180         u32 reg32;
 181
 182         reg32 = inl(tcobase + 0x04);
 183         /* set status bits are cleared by writing 1 to them */
 184         outl(reg32 & ~(1<<18), tcobase + 0x04); //  Don't clear BOOT_STS before SECOND_TO_STS
 185         if (reg32 & (1 << 18))
 186                 outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
 187
 188         return reg32;
 189 }
 190
 191
 192 static void dump_tco_status(u32 tco_sts)
 193 {
 194         printk(BIOS_DEBUG, "TCO_STS: ");
 195         if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
 196         if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
 197         if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
 198         if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
 199         if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
 200         if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
 201         if (tco_sts & (1 <<  9)) printk(BIOS_DEBUG, "DMISCI ");
 202         if (tco_sts & (1 <<  8)) printk(BIOS_DEBUG, "BIOSWR ");
 203         if (tco_sts & (1 <<  7)) printk(BIOS_DEBUG, "NEWCENTURY ");
 204         if (tco_sts & (1 <<  3)) printk(BIOS_DEBUG, "TIMEOUT ");
 205         if (tco_sts & (1 <<  2)) printk(BIOS_DEBUG, "TCO_INT ");
 206         if (tco_sts & (1 <<  1)) printk(BIOS_DEBUG, "SW_TCO ");
 207         if (tco_sts & (1 <<  0)) printk(BIOS_DEBUG, "NMI2SMI ");
 208         printk(BIOS_DEBUG, "\n");
 209 }
 210
 211
 212
 213 /**
 214  * @brief Set the EOS bit
 215  */
 216 static void smi_set_eos(void)
 217 {
 218         u8 reg8;
 219
 220         reg8 = inb(pmbase + SMI_EN);
 221         reg8 |= EOS;
 222         outb(reg8, pmbase + SMI_EN);
 223 }
 224
 225 void southbridge_smm_init(void)
 226 {
 227         u32 smi_en;
 228         u16 pm1_en;
 229         u32 gpe0_en;
 230
 231 #if CONFIG_ELOG
 232         /* Log events from chipset before clearing */
 233         pch_log_state();
 234 #endif
 235
 236         printk(BIOS_DEBUG, "Initializing southbridge SMI...");
 237
 238         pmbase = pci_read_config32(PCI_DEV(0, 0x1f, 0),
 239                                    PMBASE) & 0xff80;
 240
 241         printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
 242
 243         smi_en = inl(pmbase + SMI_EN);
 244         if (smi_en & APMC_EN) {
 245                 printk(BIOS_INFO, "SMI# handler already enabled?\n");
 246                 return;
 247         }
 248
 249         printk(BIOS_DEBUG, "\n");
 250         dump_smi_status(reset_smi_status());
 251         dump_pm1_status(reset_pm1_status());
 252         dump_gpe0_status(reset_gpe0_status());
 253         dump_alt_gp_smi_status(reset_alt_gp_smi_status());
 254         dump_tco_status(reset_tco_status());
 255
 256         /* Disable GPE0 PME_B0 */
 257         gpe0_en = inl(pmbase + GPE0_EN);
 258         gpe0_en &= ~PME_B0_EN;
 259         outl(gpe0_en, pmbase + GPE0_EN);
 260
 261         pm1_en = 0;
 262         pm1_en |= PWRBTN_EN;
 263         pm1_en |= GBL_EN;
 264         outw(pm1_en, pmbase + PM1_EN);
 265
 266         /* Enable SMI generation:
 267          *  - on TCO events
 268          *  - on APMC writes (io 0xb2)
 269          *  - on writes to SLP_EN (sleep states)
 270          *  - on writes to GBL_RLS (bios commands)
 271          * No SMIs:
 272          *  - on microcontroller writes (io 0x62/0x66)
 273          */
 274
 275         smi_en = 0; /* reset SMI enables */
 276
 277 #if 0
 278         smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN;
 279 #endif
 280         smi_en |= TCO_EN;
 281         smi_en |= APMC_EN;
 282 #if DEBUG_PERIODIC_SMIS
 283         /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using
 284          * periodic SMIs.
 285          */
 286         smi_en |= PERIODIC_EN;
 287 #endif
 288         smi_en |= SLP_SMI_EN;
 289 #if 0
 290         smi_en |= BIOS_EN;
 291 #endif
 292
 293         /* The following need to be on for SMIs to happen */
 294         smi_en |= EOS | GBL_SMI_EN;
 295
 296         outl(smi_en, pmbase + SMI_EN);
 297 }
 298
 299 void southbridge_trigger_smi(void)
 300 {
 301         /**
 302          * There are several methods of raising a controlled SMI# via
 303          * software, among them:
 304          *  - Writes to io 0xb2 (APMC)
 305          *  - Writes to the Local Apic ICR with Delivery mode SMI.
 306          *
 307          * Using the local apic is a bit more tricky. According to
 308          * AMD Family 11 Processor BKDG no destination shorthand must be
 309          * used.
 310          * The whole SMM initialization is quite a bit hardware specific, so
 311          * I'm not too worried about the better of the methods at the moment
 312          */
 313
 314         /* raise an SMI interrupt */
 315         printk(BIOS_SPEW, "  ... raise SMI#\n");
 316         outb(0x00, 0xb2);
 317 }
 318
 319 void southbridge_clear_smi_status(void)
 320 {
 321         /* Clear SMI status */
 322         reset_smi_status();
 323
 324         /* Clear PM1 status */
 325         reset_pm1_status();
 326
 327         /* Set EOS bit so other SMIs can occur. */
 328         smi_set_eos();
 329 }
 330
 331 void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
 332 {
 333         /*
 334          * Issue SMI to set the gnvs pointer in SMM.
 335          * tcg and smi1 are unused.
 336          *
 337          * EAX = APM_CNT_GNVS_UPDATE
 338          * EBX = gnvs pointer
 339          * EDX = APM_CNT
 340          */
 341         asm volatile (
 342                 "outb %%al, %%dx\n\t"
 343                 : /* ignore result */
 344                 : "a" (APM_CNT_GNVS_UPDATE),
 345                   "b" ((u32)gnvs),
 346                   "d" (APM_CNT)
 347         );
 348 }