tree: drop last paragraph of GPL copyright header
[coreboot.git] / src / southbridge / intel / ibexpeak / smbus.c
blob3b2f18c08e70464d05af244622941d30a56bd811
1 /*
2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <console/console.h>
18 #include <device/device.h>
19 #include <device/path.h>
20 #include <device/smbus.h>
21 #include <device/pci.h>
22 #include <device/pci_ids.h>
23 #include <device/pci_ops.h>
24 #include <arch/io.h>
25 #include "pch.h"
26 #include "smbus.h"
28 static void pch_smbus_init(device_t dev)
30 struct resource *res;
31 u16 reg16;
33 /* Enable clock gating */
34 reg16 = pci_read_config32(dev, 0x80);
35 reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14));
36 pci_write_config32(dev, 0x80, reg16);
38 /* Set Receive Slave Address */
39 res = find_resource(dev, PCI_BASE_ADDRESS_4);
40 if (res)
41 outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
44 static int lsmbus_read_byte(device_t dev, u8 address)
46 u16 device;
47 struct resource *res;
48 struct bus *pbus;
50 device = dev->path.i2c.device;
51 pbus = get_pbus_smbus(dev);
52 res = find_resource(pbus->dev, 0x20);
54 return do_smbus_read_byte(res->base, device, address);
57 static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
59 u16 device;
60 struct resource *res;
61 struct bus *pbus;
63 device = dev->path.i2c.device;
64 pbus = get_pbus_smbus(dev);
65 res = find_resource(pbus->dev, 0x20);
67 return do_smbus_write_byte(res->base, device, address, val);
70 static struct smbus_bus_operations lops_smbus_bus = {
71 .read_byte = lsmbus_read_byte,
72 .write_byte = lsmbus_write_byte,
75 static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
77 if (!vendor || !device) {
78 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
79 pci_read_config32(dev, PCI_VENDOR_ID));
80 } else {
81 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
82 ((device & 0xffff) << 16) | (vendor & 0xffff));
86 static struct pci_operations smbus_pci_ops = {
87 .set_subsystem = smbus_set_subsystem,
90 static void smbus_read_resources(device_t dev)
92 struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
93 res->base = SMBUS_IO_BASE;
94 res->size = 32;
95 res->limit = res->base + res->size - 1;
96 res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
97 IORESOURCE_STORED | IORESOURCE_ASSIGNED;
99 /* Also add MMIO resource */
100 res = pci_get_resource(dev, PCI_BASE_ADDRESS_0);
103 static struct device_operations smbus_ops = {
104 .read_resources = smbus_read_resources,
105 .set_resources = pci_dev_set_resources,
106 .enable_resources = pci_dev_enable_resources,
107 .scan_bus = scan_smbus,
108 .init = pch_smbus_init,
109 .ops_smbus_bus = &lops_smbus_bus,
110 .ops_pci = &smbus_pci_ops,
113 static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0x3b30, 0 };
115 static const struct pci_driver pch_smbus __pci_driver = {
116 .ops = &smbus_ops,
117 .vendor = PCI_VENDOR_ID_INTEL,
118 .devices = pci_device_ids,