src/southbridge/intel/ibexpeak/sata.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright (C) 2013 Vladimir Serbinenko
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; version 2 of
  10  * the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <arch/io.h>
  19 #include <console/console.h>
  20 #include <device/device.h>
  21 #include <device/pci.h>
  22 #include <device/pci_ids.h>
  23 #include "pch.h"
  24 #include <pc80/mc146818rtc.h>
  25 #include <acpi/sata.h>
  26
  27 typedef struct southbridge_intel_ibexpeak_config config_t;
  28
  29 static inline u32 sir_read(struct device *dev, int idx)
  30 {
  31         pci_write_config32(dev, SATA_SIRI, idx);
  32         return pci_read_config32(dev, SATA_SIRD);
  33 }
  34
  35 static inline void sir_write(struct device *dev, int idx, u32 value)
  36 {
  37         pci_write_config32(dev, SATA_SIRI, idx);
  38         pci_write_config32(dev, SATA_SIRD, value);
  39 }
  40
  41 static void sata_init(struct device *dev)
  42 {
  43         u32 reg32;
  44         u16 reg16;
  45         /* Get the chip configuration */
  46         config_t *config = dev->chip_info;
  47         u8 sata_mode;
  48
  49         printk(BIOS_DEBUG, "SATA: Initializing...\n");
  50
  51         if (config == NULL) {
  52                 printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n");
  53                 return;
  54         }
  55
  56         if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
  57                 /* Default to AHCI */
  58                 sata_mode = 0;
  59
  60         /* SATA configuration */
  61
  62         /* Enable BARs */
  63         pci_write_config16(dev, PCI_COMMAND, 0x0007);
  64
  65         if (sata_mode == 0) {
  66                 /* AHCI */
  67                 u32 *abar;
  68
  69                 printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
  70
  71                 /* Set Interrupt Line */
  72                 /* Interrupt Pin is set by D31IP.PIP */
  73                 pci_write_config8(dev, INTR_LN, 0x0b);
  74
  75                 /* Set timings */
  76                 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
  77                                    IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
  78                 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
  79                                    IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
  80
  81                 /* Sync DMA */
  82                 pci_write_config16(dev, IDE_SDMA_CNT, 0);
  83                 pci_write_config16(dev, IDE_SDMA_TIM, 0);
  84
  85                 /* Set IDE I/O Configuration */
  86                 reg32 = SIG_MODE_PRI_NORMAL;    // | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
  87                 pci_write_config32(dev, IDE_CONFIG, reg32);
  88
  89                 /* for AHCI, Port Enable is managed in memory mapped space */
  90                 reg16 = pci_read_config16(dev, 0x92);
  91                 reg16 &= ~0x3f; /* 6 ports SKU + ORM */
  92                 reg16 |= 0x8100 | config->sata_port_map;
  93                 pci_write_config16(dev, 0x92, reg16);
  94
  95                 /* SATA Initialization register */
  96                 pci_write_config32(dev, 0x94,
  97                                    ((config->
  98                                      sata_port_map ^ 0x3f) << 24) | 0x183 |
  99                                    0x40000000);
 100                 pci_write_config32(dev, 0x98, 0x00590200);
 101
 102                 /* Initialize AHCI memory-mapped space */
 103                 abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
 104                 printk(BIOS_DEBUG, "ABAR: %p\n", abar);
 105                 /* CAP (HBA Capabilities) : enable power management */
 106                 reg32 = read32(abar + 0x00);
 107                 reg32 |= 0x0c006000;    // set PSC+SSC+SALP+SSS
 108                 reg32 &= ~0x00020060;   // clear SXS+EMS+PMS
 109                 /* Set ISS, if available */
 110                 if (config->sata_interface_speed_support) {
 111                         reg32 &= ~0x00f00000;
 112                         reg32 |= (config->sata_interface_speed_support & 0x03)
 113                             << 20;
 114                 }
 115                 write32(abar + 0x00, reg32);
 116                 /* PI (Ports implemented) */
 117                 write32(abar + 0x03, config->sata_port_map);
 118                 (void)read32(abar + 0x03);      /* Read back 1 */
 119                 (void)read32(abar + 0x03);      /* Read back 2 */
 120                 /* CAP2 (HBA Capabilities Extended) */
 121                 reg32 = read32(abar + 0x09);
 122                 reg32 &= ~0x00000002;
 123                 write32(abar + 0x09, reg32);
 124                 /* VSP (Vendor Specific Register */
 125                 reg32 = read32(abar + 0x28);
 126                 reg32 &= ~0x00000005;
 127                 write32(abar + 0x28, reg32);
 128         } else {
 129                 /* IDE */
 130                 printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
 131
 132                 /* No AHCI: clear AHCI base */
 133                 pci_write_config32(dev, 0x24, 0x00000000);
 134
 135                 /* And without AHCI BAR no memory decoding */
 136                 reg16 = pci_read_config16(dev, PCI_COMMAND);
 137                 reg16 &= ~PCI_COMMAND_MEMORY;
 138                 pci_write_config16(dev, PCI_COMMAND, reg16);
 139
 140                 /* Native mode capable on both primary and secondary (0xa)
 141                  * or'ed with enabled (0x50) = 0xf
 142                  */
 143                 pci_write_config8(dev, 0x09, 0x8f);
 144
 145                 /* Set Interrupt Line */
 146                 /* Interrupt Pin is set by D31IP.PIP */
 147                 pci_write_config8(dev, INTR_LN, 0xff);
 148
 149                 /* Set timings */
 150                 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
 151                                    IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
 152                 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
 153                                    IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
 154
 155                 /* Sync DMA */
 156                 pci_write_config16(dev, IDE_SDMA_CNT, 0);
 157                 pci_write_config16(dev, IDE_SDMA_TIM, 0);
 158
 159                 /* Set IDE I/O Configuration */
 160                 reg32 = SIG_MODE_PRI_NORMAL;
 161                 pci_write_config32(dev, IDE_CONFIG, reg32);
 162
 163                 /* Port enable */
 164                 reg16 = pci_read_config16(dev, 0x92);
 165                 reg16 &= ~0x3f;
 166                 reg16 |= config->sata_port_map;
 167                 pci_write_config16(dev, 0x92, reg16);
 168
 169                 /* SATA Initialization register */
 170                 pci_write_config32(dev, 0x94,
 171                                    ((config->
 172                                      sata_port_map ^ 0x3f) << 24) | 0x183);
 173         }
 174
 175         /* Set Gen3 Transmitter settings if needed */
 176         if (config->sata_port0_gen3_tx)
 177                 pch_iobp_update(SATA_IOBP_SP0G3IR, 0,
 178                                 config->sata_port0_gen3_tx);
 179
 180         if (config->sata_port1_gen3_tx)
 181                 pch_iobp_update(SATA_IOBP_SP1G3IR, 0,
 182                                 config->sata_port1_gen3_tx);
 183
 184         /* Additional Programming Requirements */
 185         sir_write(dev, 0x04, 0x00000000);
 186         sir_write(dev, 0x28, 0x0a000033);
 187         reg32 = sir_read(dev, 0x54);
 188         reg32 &= 0xff000000;
 189         reg32 |= 0x555555;
 190         sir_write(dev, 0x54, reg32);
 191         sir_write(dev, 0x64, 0xcccccccc);
 192         reg32 = sir_read(dev, 0x68);
 193         reg32 &= 0xffff0000;
 194         reg32 |= 0xcccc;
 195         sir_write(dev, 0x68, reg32);
 196         reg32 = sir_read(dev, 0x78);
 197         reg32 &= 0x0000ffff;
 198         reg32 |= 0x88880000;
 199         sir_write(dev, 0x78, reg32);
 200         sir_write(dev, 0x84, 0x001c7000);
 201         sir_write(dev, 0x88, 0x88888888);
 202         sir_write(dev, 0xa0, 0x001c7000);
 203         // a4
 204         sir_write(dev, 0xc4, 0x0c0c0c0c);
 205         sir_write(dev, 0xc8, 0x0c0c0c0c);
 206         sir_write(dev, 0xd4, 0x10000000);
 207
 208         pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
 209         pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
 210 }
 211
 212 static void sata_enable(device_t dev)
 213 {
 214         /* Get the chip configuration */
 215         config_t *config = dev->chip_info;
 216         u16 map = 0;
 217         u8 sata_mode;
 218
 219         if (!config)
 220                 return;
 221
 222         if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
 223                 sata_mode = 0;
 224
 225         /*
 226          * Set SATA controller mode early so the resource allocator can
 227          * properly assign IO/Memory resources for the controller.
 228          */
 229         if (sata_mode == 0)
 230                 map = 0x0060;
 231
 232         map |= (config->sata_port_map ^ 0x3f) << 8;
 233
 234         pci_write_config16(dev, 0x90, map);
 235 }
 236
 237 static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 238 {
 239         if (!vendor || !device) {
 240                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 241                                    pci_read_config32(dev, PCI_VENDOR_ID));
 242         } else {
 243                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 244                                    ((device & 0xffff) << 16) | (vendor &
 245                                                                 0xffff));
 246         }
 247 }
 248
 249 static void sata_fill_ssdt(device_t dev)
 250 {
 251         config_t *config = dev->chip_info;
 252         generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map);
 253 }
 254
 255 static struct pci_operations sata_pci_ops = {
 256         .set_subsystem = sata_set_subsystem,
 257 };
 258
 259 static struct device_operations sata_ops = {
 260         .read_resources = pci_dev_read_resources,
 261         .set_resources = pci_dev_set_resources,
 262         .enable_resources = pci_dev_enable_resources,
 263         .init = sata_init,
 264         .enable = sata_enable,
 265         .acpi_fill_ssdt_generator = sata_fill_ssdt,
 266         .scan_bus = 0,
 267         .ops_pci = &sata_pci_ops,
 268 };
 269
 270 static const unsigned short pci_device_ids[] = { 0x3b28, 0x3b29, 0x3b2e, 0 };
 271
 272 static const struct pci_driver pch_sata __pci_driver = {
 273         .ops = &sata_ops,
 274         .vendor = PCI_VENDOR_ID_INTEL,
 275         .devices = pci_device_ids,
 276 };