src/southbridge/intel/ibexpeak/pch.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright (C) 2012 The Chromium OS Authors.  All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
  18 #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
  19
  20 /* PCH types */
  21 #define PCH_TYPE_CPT       0x1c /* CougarPoint */
  22 #define PCH_TYPE_PPT       0x1e /* IvyBridge */
  23 #define PCH_TYPE_MOBILE5   0x3b
  24
  25 /* PCH stepping values for LPC device */
  26 #define PCH_STEP_A0     0
  27 #define PCH_STEP_A1     1
  28 #define PCH_STEP_B0     2
  29 #define PCH_STEP_B1     3
  30 #define PCH_STEP_B2     4
  31 #define PCH_STEP_B3     5
  32
  33 /*
  34  * It does not matter where we put the SMBus I/O base, as long as we
  35  * keep it consistent and don't interfere with other devices.  Stage2
  36  * will relocate this anyways.
  37  * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
  38  * again. But handling static BARs is a generic problem that should be
  39  * solved in the device allocator.
  40  */
  41 #define SMBUS_IO_BASE           0x0400
  42 #define SMBUS_SLAVE_ADDR        0x24
  43 /* TODO Make sure these don't get changed by stage2 */
  44 #define DEFAULT_GPIOBASE        0x0480
  45 #define DEFAULT_PMBASE          0x0500
  46
  47 #ifndef __ACPI__
  48 #define DEFAULT_RCBA            ((u8 *)0xfed1c000)
  49 #else
  50 #define DEFAULT_RCBA            0xfed1c000
  51 #endif
  52
  53 #ifndef __ACPI__
  54 #define DEBUG_PERIODIC_SMIS 0
  55
  56 #if defined (__SMM__) && !defined(__ASSEMBLER__)
  57 void intel_pch_finalize_smm(void);
  58 #endif
  59
  60 #if !defined(__ASSEMBLER__)
  61 #if !defined(__PRE_RAM__)
  62 #if !defined(__SMM__)
  63 #include "chip.h"
  64 void pch_enable(device_t dev);
  65 #endif
  66 int pch_silicon_revision(void);
  67 int pch_silicon_type(void);
  68 int pch_silicon_supported(int type, int rev);
  69 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
  70 void gpi_route_interrupt(u8 gpi, u8 mode);
  71 #if CONFIG_ELOG
  72 void pch_log_state(void);
  73 #endif
  74 #else /* __PRE_RAM__ */
  75 void enable_smbus(void);
  76 void enable_usb_bar(void);
  77 int smbus_read_byte(unsigned device, unsigned address);
  78 int smbus_write_byte(unsigned device, unsigned address, u8 data);
  79 int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf);
  80 int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf);
  81 int early_spi_read(u32 offset, u32 size, u8 *buffer);
  82 void early_thermal_init(void);
  83 void southbridge_configure_default_intmap(void);
  84 #endif
  85 #endif
  86
  87 #define MAINBOARD_POWER_OFF     0
  88 #define MAINBOARD_POWER_ON      1
  89 #define MAINBOARD_POWER_KEEP    2
  90
  91 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
  92 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
  93 #endif
  94
  95 /* PCI Configuration Space (D30:F0): PCI2PCI */
  96 #define PSTS    0x06
  97 #define SMLT    0x1b
  98 #define SECSTS  0x1e
  99 #define INTR    0x3c
 100 #define BCTRL   0x3e
 101 #define   SBR   (1 << 6)
 102 #define   SEE   (1 << 1)
 103 #define   PERE  (1 << 0)
 104
 105 #define PCH_EHCI1_DEV           PCI_DEV(0, 0x1d, 0)
 106 #define PCH_EHCI2_DEV           PCI_DEV(0, 0x1a, 0)
 107 #define PCH_XHCI_DEV            PCI_DEV(0, 0x14, 0)
 108 #define PCH_ME_DEV              PCI_DEV(0, 0x16, 0)
 109 #define PCH_PCIE_DEV_SLOT       28
 110
 111 /* PCI Configuration Space (D31:F0): LPC */
 112 #define PCH_LPC_DEV             PCI_DEV(0, 0x1f, 0)
 113 #define SERIRQ_CNTL             0x64
 114
 115 #define GEN_PMCON_1             0xa0
 116 #define GEN_PMCON_2             0xa2
 117 #define GEN_PMCON_3             0xa4
 118 #define ETR3                    0xac
 119 #define  ETR3_CWORWRE           (1 << 18)
 120 #define  ETR3_CF9GR             (1 << 20)
 121
 122 /* GEN_PMCON_3 bits */
 123 #define RTC_BATTERY_DEAD        (1 << 2)
 124 #define RTC_POWER_FAILED        (1 << 1)
 125 #define SLEEP_AFTER_POWER_FAIL  (1 << 0)
 126
 127 #define PMBASE                  0x40
 128 #define ACPI_CNTL               0x44
 129 #define   ACPI_EN               (1 << 7)
 130 #define BIOS_CNTL               0xDC
 131 #define GPIO_BASE               0x48 /* LPC GPIO Base Address Register */
 132 #define GPIO_CNTL               0x4C /* LPC GPIO Control Register */
 133
 134 #define GPIO_ROUT               0xb8
 135 #define   GPI_DISABLE           0x00
 136 #define   GPI_IS_SMI            0x01
 137 #define   GPI_IS_SCI            0x02
 138 #define   GPI_IS_NMI            0x03
 139
 140 #define PIRQA_ROUT              0x60
 141 #define PIRQB_ROUT              0x61
 142 #define PIRQC_ROUT              0x62
 143 #define PIRQD_ROUT              0x63
 144 #define PIRQE_ROUT              0x68
 145 #define PIRQF_ROUT              0x69
 146 #define PIRQG_ROUT              0x6A
 147 #define PIRQH_ROUT              0x6B
 148
 149 #define LPC_IO_DEC              0x80 /* IO Decode Ranges Register */
 150 #define LPC_EN                  0x82 /* LPC IF Enables Register */
 151 #define  CNF2_LPC_EN            (1 << 13) /* 0x4e/0x4f */
 152 #define  CNF1_LPC_EN            (1 << 12) /* 0x2e/0x2f */
 153 #define  MC_LPC_EN              (1 << 11) /* 0x62/0x66 */
 154 #define  KBC_LPC_EN             (1 << 10) /* 0x60/0x64 */
 155 #define  GAMEH_LPC_EN           (1 << 9)  /* 0x208/0x20f */
 156 #define  GAMEL_LPC_EN           (1 << 8)  /* 0x200/0x207 */
 157 #define  FDD_LPC_EN             (1 << 3)  /* LPC_IO_DEC[12] */
 158 #define  LPT_LPC_EN             (1 << 2)  /* LPC_IO_DEC[9:8] */
 159 #define  COMB_LPC_EN            (1 << 1)  /* LPC_IO_DEC[6:4] */
 160 #define  COMA_LPC_EN            (1 << 0)  /* LPC_IO_DEC[3:2] */
 161 #define LPC_GEN1_DEC            0x84 /* LPC IF Generic Decode Range 1 */
 162 #define LPC_GEN2_DEC            0x88 /* LPC IF Generic Decode Range 2 */
 163 #define LPC_GEN3_DEC            0x8c /* LPC IF Generic Decode Range 3 */
 164 #define LPC_GEN4_DEC            0x90 /* LPC IF Generic Decode Range 4 */
 165
 166 /* PCI Configuration Space (D31:F1): IDE */
 167 #define PCH_IDE_DEV             PCI_DEV(0, 0x1f, 1)
 168 #define PCH_SATA_DEV            PCI_DEV(0, 0x1f, 2)
 169 #define PCH_SATA2_DEV           PCI_DEV(0, 0x1f, 5)
 170 #define INTR_LN                 0x3c
 171 #define IDE_TIM_PRI             0x40    /* IDE timings, primary */
 172 #define   IDE_DECODE_ENABLE     (1 << 15)
 173 #define   IDE_SITRE             (1 << 14)
 174 #define   IDE_ISP_5_CLOCKS      (0 << 12)
 175 #define   IDE_ISP_4_CLOCKS      (1 << 12)
 176 #define   IDE_ISP_3_CLOCKS      (2 << 12)
 177 #define   IDE_RCT_4_CLOCKS      (0 <<  8)
 178 #define   IDE_RCT_3_CLOCKS      (1 <<  8)
 179 #define   IDE_RCT_2_CLOCKS      (2 <<  8)
 180 #define   IDE_RCT_1_CLOCKS      (3 <<  8)
 181 #define   IDE_DTE1              (1 <<  7)
 182 #define   IDE_PPE1              (1 <<  6)
 183 #define   IDE_IE1               (1 <<  5)
 184 #define   IDE_TIME1             (1 <<  4)
 185 #define   IDE_DTE0              (1 <<  3)
 186 #define   IDE_PPE0              (1 <<  2)
 187 #define   IDE_IE0               (1 <<  1)
 188 #define   IDE_TIME0             (1 <<  0)
 189 #define IDE_TIM_SEC             0x42    /* IDE timings, secondary */
 190
 191 #define IDE_SDMA_CNT            0x48    /* Synchronous DMA control */
 192 #define   IDE_SSDE1             (1 <<  3)
 193 #define   IDE_SSDE0             (1 <<  2)
 194 #define   IDE_PSDE1             (1 <<  1)
 195 #define   IDE_PSDE0             (1 <<  0)
 196
 197 #define IDE_SDMA_TIM            0x4a
 198
 199 #define IDE_CONFIG              0x54    /* IDE I/O Configuration Register */
 200 #define   SIG_MODE_SEC_NORMAL   (0 << 18)
 201 #define   SIG_MODE_SEC_TRISTATE (1 << 18)
 202 #define   SIG_MODE_SEC_DRIVELOW (2 << 18)
 203 #define   SIG_MODE_PRI_NORMAL   (0 << 16)
 204 #define   SIG_MODE_PRI_TRISTATE (1 << 16)
 205 #define   SIG_MODE_PRI_DRIVELOW (2 << 16)
 206 #define   FAST_SCB1             (1 << 15)
 207 #define   FAST_SCB0             (1 << 14)
 208 #define   FAST_PCB1             (1 << 13)
 209 #define   FAST_PCB0             (1 << 12)
 210 #define   SCB1                  (1 <<  3)
 211 #define   SCB0                  (1 <<  2)
 212 #define   PCB1                  (1 <<  1)
 213 #define   PCB0                  (1 <<  0)
 214
 215 #define SATA_SIRI               0xa0 /* SATA Indexed Register Index */
 216 #define SATA_SIRD               0xa4 /* SATA Indexed Register Data */
 217 #define SATA_SP                 0xd0 /* Scratchpad */
 218
 219 /* SATA IOBP Registers */
 220 #define SATA_IOBP_SP0G3IR       0xea000151
 221 #define SATA_IOBP_SP1G3IR       0xea000051
 222
 223 /* PCI Configuration Space (D31:F3): SMBus */
 224 #define PCH_SMBUS_DEV           PCI_DEV(0, 0x1f, 3)
 225 #define SMB_BASE                0x20
 226 #define HOSTC                   0x40
 227 #define SMB_RCV_SLVA            0x09
 228
 229 /* HOSTC bits */
 230 #define I2C_EN                  (1 << 2)
 231 #define SMB_SMI_EN              (1 << 1)
 232 #define HST_EN                  (1 << 0)
 233
 234 /* SMBus I/O bits. */
 235 #define SMBHSTSTAT              0x0
 236 #define SMBHSTCTL               0x2
 237 #define SMBHSTCMD               0x3
 238 #define SMBXMITADD              0x4
 239 #define SMBHSTDAT0              0x5
 240 #define SMBHSTDAT1              0x6
 241 #define SMBBLKDAT               0x7
 242 #define SMBTRNSADD              0x9
 243 #define SMBSLVDATA              0xa
 244 #define SMLINK_PIN_CTL          0xe
 245 #define SMBUS_PIN_CTL           0xf
 246
 247 #define SMBUS_TIMEOUT           (10 * 1000 * 100)
 248
 249
 250 /* Southbridge IO BARs */
 251
 252 #define GPIOBASE                0x48
 253
 254 #define PMBASE          0x40
 255
 256 /* Root Complex Register Block */
 257 #define RCBA            0xf0
 258
 259 #define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
 260 #define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
 261 #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
 262
 263 #define RCBA_AND_OR(bits, x, and, or) \
 264         RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
 265 #define RCBA8_AND_OR(x, and, or)  RCBA_AND_OR(8, x, and, or)
 266 #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
 267 #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
 268 #define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
 269
 270 #define VCH             0x0000  /* 32bit */
 271 #define VCAP1           0x0004  /* 32bit */
 272 #define VCAP2           0x0008  /* 32bit */
 273 #define PVC             0x000c  /* 16bit */
 274 #define PVS             0x000e  /* 16bit */
 275
 276 #define V0CAP           0x0010  /* 32bit */
 277 #define V0CTL           0x0014  /* 32bit */
 278 #define V0STS           0x001a  /* 16bit */
 279
 280 #define V1CAP           0x001c  /* 32bit */
 281 #define V1CTL           0x0020  /* 32bit */
 282 #define V1STS           0x0026  /* 16bit */
 283
 284 #define RCTCL           0x0100  /* 32bit */
 285 #define ESD             0x0104  /* 32bit */
 286 #define ULD             0x0110  /* 32bit */
 287 #define ULBA            0x0118  /* 64bit */
 288
 289 #define RP1D            0x0120  /* 32bit */
 290 #define RP1BA           0x0128  /* 64bit */
 291 #define RP2D            0x0130  /* 32bit */
 292 #define RP2BA           0x0138  /* 64bit */
 293 #define RP3D            0x0140  /* 32bit */
 294 #define RP3BA           0x0148  /* 64bit */
 295 #define RP4D            0x0150  /* 32bit */
 296 #define RP4BA           0x0158  /* 64bit */
 297 #define HDD             0x0160  /* 32bit */
 298 #define HDBA            0x0168  /* 64bit */
 299 #define RP5D            0x0170  /* 32bit */
 300 #define RP5BA           0x0178  /* 64bit */
 301 #define RP6D            0x0180  /* 32bit */
 302 #define RP6BA           0x0188  /* 64bit */
 303
 304 #define RPC             0x0400  /* 32bit */
 305 #define RPFN            0x0404  /* 32bit */
 306
 307 /* Root Port configuratinon space hide */
 308 #define RPFN_HIDE(port)         (1 << (((port) * 4) + 3))
 309 /* Get the function number assigned to a Root Port */
 310 #define RPFN_FNGET(reg,port)    (((reg) >> ((port) * 4)) & 7)
 311 /* Set the function number for a Root Port */
 312 #define RPFN_FNSET(port,func)   (((func) & 7) << ((port) * 4))
 313 /* Root Port function number mask */
 314 #define RPFN_FNMASK(port)       (7 << ((port) * 4))
 315
 316 #define TRSR            0x1e00  /*  8bit */
 317 #define TRCR            0x1e10  /* 64bit */
 318 #define TWDR            0x1e18  /* 64bit */
 319
 320 #define IOTR0           0x1e80  /* 64bit */
 321 #define IOTR1           0x1e88  /* 64bit */
 322 #define IOTR2           0x1e90  /* 64bit */
 323 #define IOTR3           0x1e98  /* 64bit */
 324
 325 #define TCTL            0x3000  /*  8bit */
 326
 327 #define NOINT           0
 328 #define INTA            1
 329 #define INTB            2
 330 #define INTC            3
 331 #define INTD            4
 332
 333 #define DIR_IDR         12      /* Interrupt D Pin Offset */
 334 #define DIR_ICR         8       /* Interrupt C Pin Offset */
 335 #define DIR_IBR         4       /* Interrupt B Pin Offset */
 336 #define DIR_IAR         0       /* Interrupt A Pin Offset */
 337
 338 #define PIRQA           0
 339 #define PIRQB           1
 340 #define PIRQC           2
 341 #define PIRQD           3
 342 #define PIRQE           4
 343 #define PIRQF           5
 344 #define PIRQG           6
 345 #define PIRQH           7
 346
 347 /* IO Buffer Programming */
 348 #define IOBPIRI         0x2330
 349 #define IOBPD           0x2334
 350 #define IOBPS           0x2338
 351 #define  IOBPS_RW_BX    ((1 << 9)|(1 << 10))
 352 #define  IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
 353 #define  IOBPS_READ_AX  ((1 << 8)|(1 << 9)|(1 << 10))
 354
 355 #define D31IP           0x3100  /* 32bit */
 356 #define D31IP_TTIP      24      /* Thermal Throttle Pin */
 357 #define D31IP_SIP2      20      /* SATA Pin 2 */
 358 #define D31IP_UNKIP     16
 359 #define D31IP_SMIP      12      /* SMBUS Pin */
 360 #define D31IP_SIP       8       /* SATA Pin */
 361 #define D30IP           0x3104  /* 32bit */
 362 #define D30IP_PIP       0       /* PCI Bridge Pin */
 363 #define D29IP           0x3108  /* 32bit */
 364 #define D29IP_E1P       0       /* EHCI #1 Pin */
 365 #define D28IP           0x310c  /* 32bit */
 366 #define D28IP_P8IP      28      /* PCI Express Port 8 */
 367 #define D28IP_P7IP      24      /* PCI Express Port 7 */
 368 #define D28IP_P6IP      20      /* PCI Express Port 6 */
 369 #define D28IP_P5IP      16      /* PCI Express Port 5 */
 370 #define D28IP_P4IP      12      /* PCI Express Port 4 */
 371 #define D28IP_P3IP      8       /* PCI Express Port 3 */
 372 #define D28IP_P2IP      4       /* PCI Express Port 2 */
 373 #define D28IP_P1IP      0       /* PCI Express Port 1 */
 374 #define D27IP           0x3110  /* 32bit */
 375 #define D27IP_ZIP       0       /* HD Audio Pin */
 376 #define D26IP           0x3114  /* 32bit */
 377 #define D26IP_E2P       0       /* EHCI #2 Pin */
 378 #define D25IP           0x3118  /* 32bit */
 379 #define D25IP_LIP       0       /* GbE LAN Pin */
 380 #define D22IP           0x3124  /* 32bit */
 381 #define D22IP_KTIP      12      /* KT Pin */
 382 #define D22IP_IDERIP    8       /* IDE-R Pin */
 383 #define D22IP_MEI2IP    4       /* MEI #2 Pin */
 384 #define D22IP_MEI1IP    0       /* MEI #1 Pin */
 385 #define D20IP           0x3128  /* 32bit */
 386 #define D20IP_XHCIIP    0
 387 #define D31IR           0x3140  /* 16bit */
 388 #define D30IR           0x3142  /* 16bit */
 389 #define D29IR           0x3144  /* 16bit */
 390 #define D28IR           0x3146  /* 16bit */
 391 #define D27IR           0x3148  /* 16bit */
 392 #define D26IR           0x314c  /* 16bit */
 393 #define D25IR           0x3150  /* 16bit */
 394 #define D22IR           0x315c  /* 16bit */
 395 #define D20IR           0x3160  /* 16bit */
 396 #define OIC             0x31fe  /* 16bit */
 397 #define SOFT_RESET_CTRL 0x38f4
 398 #define SOFT_RESET_DATA 0x38f8
 399
 400 #define DIR_ROUTE(x,a,b,c,d) \
 401   RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
 402                ((b) << DIR_IBR) | ((a) << DIR_IAR))
 403
 404 #define RC              0x3400  /* 32bit */
 405 #define HPTC            0x3404  /* 32bit */
 406 #define GCS             0x3410  /* 32bit */
 407 #define BUC             0x3414  /* 32bit */
 408 #define PCH_DISABLE_GBE         (1 << 5)
 409 #define FD              0x3418  /* 32bit */
 410 #define DISPBDF         0x3424  /* 16bit */
 411 #define FD2             0x3428  /* 32bit */
 412 #define CG              0x341c  /* 32bit */
 413
 414 /* Function Disable 1 RCBA 0x3418 */
 415 #define PCH_DISABLE_ALWAYS      ((1 << 0)|(1 << 26))
 416 #define PCH_DISABLE_P2P         (1 << 1)
 417 #define PCH_DISABLE_SATA1       (1 << 2)
 418 #define PCH_DISABLE_SMBUS       (1 << 3)
 419 #define PCH_DISABLE_HD_AUDIO    (1 << 4)
 420 #define PCH_DISABLE_EHCI2       (1 << 13)
 421 #define PCH_DISABLE_LPC         (1 << 14)
 422 #define PCH_DISABLE_EHCI1       (1 << 15)
 423 #define PCH_DISABLE_PCIE(x)     (1 << (16 + x))
 424 #define PCH_DISABLE_THERMAL     (1 << 24)
 425 #define PCH_DISABLE_SATA2       (1 << 25)
 426 #define PCH_DISABLE_XHCI        (1 << 27)
 427
 428 /* Function Disable 2 RCBA 0x3428 */
 429 #define PCH_DISABLE_KT          (1 << 4)
 430 #define PCH_DISABLE_IDER        (1 << 3)
 431 #define PCH_DISABLE_MEI2        (1 << 2)
 432 #define PCH_DISABLE_MEI1        (1 << 1)
 433 #define PCH_ENABLE_DBDF         (1 << 0)
 434
 435 /* ICH7 GPIOBASE */
 436 #define GPIO_USE_SEL    0x00
 437 #define GP_IO_SEL       0x04
 438 #define GP_LVL          0x0c
 439 #define GPO_BLINK       0x18
 440 #define GPI_INV         0x2c
 441 #define GPIO_USE_SEL2   0x30
 442 #define GP_IO_SEL2      0x34
 443 #define GP_LVL2         0x38
 444 #define GPIO_USE_SEL3   0x40
 445 #define GP_IO_SEL3      0x44
 446 #define GP_LVL3         0x48
 447 #define GP_RST_SEL1     0x60
 448 #define GP_RST_SEL2     0x64
 449 #define GP_RST_SEL3     0x68
 450
 451 /* ICH7 PMBASE */
 452 #define PM1_STS         0x00
 453 #define   WAK_STS       (1 << 15)
 454 #define   PCIEXPWAK_STS (1 << 14)
 455 #define   PRBTNOR_STS   (1 << 11)
 456 #define   RTC_STS       (1 << 10)
 457 #define   PWRBTN_STS    (1 << 8)
 458 #define   GBL_STS       (1 << 5)
 459 #define   BM_STS        (1 << 4)
 460 #define   TMROF_STS     (1 << 0)
 461 #define PM1_EN          0x02
 462 #define   PCIEXPWAK_DIS (1 << 14)
 463 #define   RTC_EN        (1 << 10)
 464 #define   PWRBTN_EN     (1 << 8)
 465 #define   GBL_EN        (1 << 5)
 466 #define   TMROF_EN      (1 << 0)
 467 #define PM1_CNT         0x04
 468 #define   SLP_EN        (1 << 13)
 469 #define   SLP_TYP       (7 << 10)
 470 #define    SLP_TYP_S0   0
 471 #define    SLP_TYP_S1   1
 472 #define    SLP_TYP_S3   5
 473 #define    SLP_TYP_S4   6
 474 #define    SLP_TYP_S5   7
 475 #define   GBL_RLS       (1 << 2)
 476 #define   BM_RLD        (1 << 1)
 477 #define   SCI_EN        (1 << 0)
 478 #define PM1_TMR         0x08
 479 #define PROC_CNT        0x10
 480 #define LV2             0x14
 481 #define LV3             0x15
 482 #define LV4             0x16
 483 #define PM2_CNT         0x50 // mobile only
 484 #define GPE0_STS        0x20
 485 #define   PME_B0_STS    (1 << 13)
 486 #define   PME_STS       (1 << 11)
 487 #define   BATLOW_STS    (1 << 10)
 488 #define   PCI_EXP_STS   (1 << 9)
 489 #define   RI_STS        (1 << 8)
 490 #define   SMB_WAK_STS   (1 << 7)
 491 #define   TCOSCI_STS    (1 << 6)
 492 #define   SWGPE_STS     (1 << 2)
 493 #define   HOT_PLUG_STS  (1 << 1)
 494 #define GPE0_EN         0x28
 495 #define   PME_B0_EN     (1 << 13)
 496 #define   PME_EN        (1 << 11)
 497 #define   TCOSCI_EN     (1 << 6)
 498 #define SMI_EN          0x30
 499 #define   INTEL_USB2_EN  (1 << 18) // Intel-Specific USB2 SMI logic
 500 #define   LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
 501 #define   PERIODIC_EN    (1 << 14) // SMI on PERIODIC_STS in SMI_STS
 502 #define   TCO_EN         (1 << 13) // Enable TCO Logic (BIOSWE et al)
 503 #define   MCSMI_EN       (1 << 11) // Trap microcontroller range access
 504 #define   BIOS_RLS       (1 <<  7) // asserts SCI on bit set
 505 #define   SWSMI_TMR_EN   (1 <<  6) // start software smi timer on bit set
 506 #define   APMC_EN        (1 <<  5) // Writes to APM_CNT cause SMI#
 507 #define   SLP_SMI_EN     (1 <<  4) // Write to SLP_EN in PM1_CNT asserts SMI#
 508 #define   LEGACY_USB_EN  (1 <<  3) // Legacy USB circuit SMI logic
 509 #define   BIOS_EN        (1 <<  2) // Assert SMI# on setting GBL_RLS bit
 510 #define   EOS            (1 <<  1) // End of SMI (deassert SMI#)
 511 #define   GBL_SMI_EN     (1 <<  0) // SMI# generation at all?
 512 #define SMI_STS         0x34
 513 #define ALT_GP_SMI_EN   0x38
 514 #define ALT_GP_SMI_STS  0x3a
 515 #define GPE_CNTL        0x42
 516 #define DEVACT_STS      0x44
 517 #define SS_CNT          0x50
 518 #define C3_RES          0x54
 519 #define TCO1_STS        0x64
 520 #define   DMISCI_STS    (1 << 9)
 521 #define TCO2_STS        0x66
 522
 523 /*
 524  * SPI Opcode Menu setup for SPIBAR lockdown
 525  * should support most common flash chips.
 526  */
 527
 528 #define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
 529 #define SPI_OPTYPE_0 0x01 /* Write, no address */
 530
 531 #define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
 532 #define SPI_OPTYPE_1 0x03 /* Write, address required */
 533
 534 #define SPI_OPMENU_2 0x03 /* READ: Read Data */
 535 #define SPI_OPTYPE_2 0x02 /* Read, address required */
 536
 537 #define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
 538 #define SPI_OPTYPE_3 0x00 /* Read, no address */
 539
 540 #define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
 541 #define SPI_OPTYPE_4 0x03 /* Write, address required */
 542
 543 #define SPI_OPMENU_5 0x9f /* RDID: Read ID */
 544 #define SPI_OPTYPE_5 0x00 /* Read, no address */
 545
 546 #define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
 547 #define SPI_OPTYPE_6 0x03 /* Write, address required */
 548
 549 #define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
 550 #define SPI_OPTYPE_7 0x02 /* Read, address required */
 551
 552 #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
 553                           (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
 554 #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
 555                           (SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
 556
 557 #define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
 558                     (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) |  \
 559                     (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) |   \
 560                     (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
 561
 562 #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
 563
 564 #define SPIBAR_HSFS                 0x3804   /* SPI hardware sequence status */
 565 #define  SPIBAR_HSFS_SCIP           (1 << 5) /* SPI Cycle In Progress */
 566 #define  SPIBAR_HSFS_AEL            (1 << 2) /* SPI Access Error Log */
 567 #define  SPIBAR_HSFS_FCERR          (1 << 1) /* SPI Flash Cycle Error */
 568 #define  SPIBAR_HSFS_FDONE          (1 << 0) /* SPI Flash Cycle Done */
 569 #define SPIBAR_HSFC                 0x3806   /* SPI hardware sequence control */
 570 #define  SPIBAR_HSFC_BYTE_COUNT(c)  (((c - 1) & 0x3f) << 8)
 571 #define  SPIBAR_HSFC_CYCLE_READ     (0 << 1) /* Read cycle */
 572 #define  SPIBAR_HSFC_CYCLE_WRITE    (2 << 1) /* Write cycle */
 573 #define  SPIBAR_HSFC_CYCLE_ERASE    (3 << 1) /* Erase cycle */
 574 #define  SPIBAR_HSFC_GO             (1 << 0) /* GO: start SPI transaction */
 575 #define SPIBAR_FADDR                0x3808   /* SPI flash address */
 576 #define SPIBAR_FDATA(n)             (0x3810 + (4 * n)) /* SPI flash data */
 577
 578 #endif /* __ACPI__ */
 579 #endif                          /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */