tree: drop last paragraph of GPL copyright header
[coreboot.git] / src / southbridge / intel / i82801ix / smbus.c
blob211372237fc2f4bc36d60d4bd27c01c6a85fb44e
1 /*
2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <console/console.h>
18 #include <device/device.h>
19 #include <device/path.h>
20 #include <device/smbus.h>
21 #include <device/pci.h>
22 #include <device/pci_ids.h>
23 #include <device/pci_ops.h>
24 #include <arch/io.h>
25 #include "smbus.h"
27 static void pch_smbus_init(device_t dev)
29 u16 reg16;
31 /* Enable clock gating */
32 reg16 = pci_read_config16(dev, 0x80);
33 reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14));
34 pci_write_config16(dev, 0x80, reg16);
37 static int lsmbus_read_byte(device_t dev, u8 address)
39 u16 device;
40 struct resource *res;
41 struct bus *pbus;
43 device = dev->path.i2c.device;
44 pbus = get_pbus_smbus(dev);
45 res = find_resource(pbus->dev, 0x20);
47 return do_smbus_read_byte(res->base, device, address);
50 static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
52 u16 device;
53 struct resource *res;
54 struct bus *pbus;
56 device = dev->path.i2c.device;
57 pbus = get_pbus_smbus(dev);
58 res = find_resource(pbus->dev, 0x20);
60 return do_smbus_write_byte(res->base, device, address, val);
63 static struct smbus_bus_operations lops_smbus_bus = {
64 .read_byte = lsmbus_read_byte,
65 .write_byte = lsmbus_write_byte,
68 static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
70 if (!vendor || !device) {
71 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
72 pci_read_config32(dev, PCI_VENDOR_ID));
73 } else {
74 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
75 ((device & 0xffff) << 16) | (vendor & 0xffff));
79 static struct pci_operations smbus_pci_ops = {
80 .set_subsystem = smbus_set_subsystem,
83 static void smbus_read_resources(device_t dev)
85 struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
86 res->base = SMBUS_IO_BASE;
87 res->size = 32;
88 res->limit = res->base + res->size - 1;
89 res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
90 IORESOURCE_STORED | IORESOURCE_ASSIGNED;
92 /* Also add MMIO resource */
93 res = pci_get_resource(dev, PCI_BASE_ADDRESS_0);
96 static struct device_operations smbus_ops = {
97 .read_resources = smbus_read_resources,
98 .set_resources = pci_dev_set_resources,
99 .enable_resources = pci_dev_enable_resources,
100 .scan_bus = scan_smbus,
101 .init = pch_smbus_init,
102 .ops_smbus_bus = &lops_smbus_bus,
103 .ops_pci = &smbus_pci_ops,
106 static const unsigned short pci_device_ids[] = { 0x2930, 0 };
108 static const struct pci_driver pch_smbus __pci_driver = {
109 .ops = &smbus_ops,
110 .vendor = PCI_VENDOR_ID_INTEL,
111 .devices = pci_device_ids,