src/southbridge/intel/i82801gx/smihandler.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <types.h>
  18 #include <arch/io.h>
  19 #include <console/console.h>
  20 #include <cpu/x86/cache.h>
  21 #include <cpu/x86/smm.h>
  22 #include <device/pci_def.h>
  23 #include <halt.h>
  24 #include <pc80/mc146818rtc.h>
  25 #include "i82801gx.h"
  26
  27 /* I945 */
  28 #define SMRAM           0x9d
  29 #define   D_OPEN        (1 << 6)
  30 #define   D_CLS         (1 << 5)
  31 #define   D_LCK         (1 << 4)
  32 #define   G_SMRANE      (1 << 3)
  33 #define   C_BASE_SEG    ((0 << 2) | (1 << 1) | (0 << 0))
  34
  35 #include "nvs.h"
  36
  37 /* While we read PMBASE dynamically in case it changed, let's
  38  * initialize it with a sane value
  39  */
  40 u16 pmbase = DEFAULT_PMBASE;
  41 u8 smm_initialized = 0;
  42
  43 /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
  44  * by coreboot.
  45  */
  46 global_nvs_t *gnvs = (global_nvs_t *)0x0;
  47
  48 static void alt_gpi_mask(u16 clr, u16 set)
  49 {
  50         u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN);
  51         alt_gp &= ~clr;
  52         alt_gp |= set;
  53         outw(alt_gp, pmbase + ALT_GP_SMI_EN);
  54 }
  55
  56 static void gpe0_mask(u32 clr, u32 set)
  57 {
  58         u32 gpe0 = inl(pmbase + GPE0_EN);
  59         gpe0 &= ~clr;
  60         gpe0 |= set;
  61         outl(gpe0, pmbase + GPE0_EN);
  62 }
  63
  64 void gpi_route_interrupt(u8 gpi, u8 mode)
  65 {
  66         u32 gpi_rout;
  67         if (gpi >= 16)
  68                 return;
  69
  70         alt_gpi_mask(1 << gpi, 0);
  71         gpe0_mask(1 << (gpi+16), 0);
  72
  73         gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
  74         gpi_rout &= ~(3 << (2 * gpi));
  75         gpi_rout |= ((mode & 3) << (2 * gpi));
  76         pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout);
  77
  78         if (mode == GPI_IS_SCI)
  79                 gpe0_mask(0, 1 << (gpi+16));
  80         else if (mode == GPI_IS_SMI)
  81                 alt_gpi_mask(0, 1 << gpi);
  82 }
  83
  84 /**
  85  * @brief read and clear PM1_STS
  86  * @return PM1_STS register
  87  */
  88 static u16 reset_pm1_status(void)
  89 {
  90         u16 reg16;
  91
  92         reg16 = inw(pmbase + PM1_STS);
  93         /* set status bits are cleared by writing 1 to them */
  94         outw(reg16, pmbase + PM1_STS);
  95
  96         return reg16;
  97 }
  98
  99 static void dump_pm1_status(u16 pm1_sts)
 100 {
 101         printk(BIOS_SPEW, "PM1_STS: ");
 102         if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
 103         if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
 104         if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
 105         if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
 106         if (pm1_sts & (1 <<  8)) printk(BIOS_SPEW, "PWRBTN ");
 107         if (pm1_sts & (1 <<  5)) printk(BIOS_SPEW, "GBL ");
 108         if (pm1_sts & (1 <<  4)) printk(BIOS_SPEW, "BM ");
 109         if (pm1_sts & (1 <<  0)) printk(BIOS_SPEW, "TMROF ");
 110         printk(BIOS_SPEW, "\n");
 111         int reg16 = inw(pmbase + PM1_EN);
 112         printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
 113 }
 114
 115 /**
 116  * @brief read and clear SMI_STS
 117  * @return SMI_STS register
 118  */
 119 static u32 reset_smi_status(void)
 120 {
 121         u32 reg32;
 122
 123         reg32 = inl(pmbase + SMI_STS);
 124         /* set status bits are cleared by writing 1 to them */
 125         outl(reg32, pmbase + SMI_STS);
 126
 127         return reg32;
 128 }
 129
 130 static void dump_smi_status(u32 smi_sts)
 131 {
 132         printk(BIOS_DEBUG, "SMI_STS: ");
 133         if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
 134         if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
 135         if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
 136         if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
 137         if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
 138         if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
 139         if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
 140         if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
 141         if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
 142         if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
 143         if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
 144         if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
 145         if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
 146         if (smi_sts & (1 <<  9)) printk(BIOS_DEBUG, "GPE0 ");
 147         if (smi_sts & (1 <<  8)) printk(BIOS_DEBUG, "PM1 ");
 148         if (smi_sts & (1 <<  6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
 149         if (smi_sts & (1 <<  5)) printk(BIOS_DEBUG, "APM ");
 150         if (smi_sts & (1 <<  4)) printk(BIOS_DEBUG, "SLP_SMI ");
 151         if (smi_sts & (1 <<  3)) printk(BIOS_DEBUG, "LEGACY_USB ");
 152         if (smi_sts & (1 <<  2)) printk(BIOS_DEBUG, "BIOS ");
 153         printk(BIOS_DEBUG, "\n");
 154 }
 155
 156
 157 /**
 158  * @brief read and clear GPE0_STS
 159  * @return GPE0_STS register
 160  */
 161 static u32 reset_gpe0_status(void)
 162 {
 163         u32 reg32;
 164
 165         reg32 = inl(pmbase + GPE0_STS);
 166         /* set status bits are cleared by writing 1 to them */
 167         outl(reg32, pmbase + GPE0_STS);
 168
 169         return reg32;
 170 }
 171
 172 static void dump_gpe0_status(u32 gpe0_sts)
 173 {
 174         int i;
 175         printk(BIOS_DEBUG, "GPE0_STS: ");
 176         for (i=31; i>= 16; i--) {
 177                 if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
 178         }
 179         if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
 180         if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
 181         if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
 182         if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
 183         if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
 184         if (gpe0_sts & (1 <<  9)) printk(BIOS_DEBUG, "PCI_EXP ");
 185         if (gpe0_sts & (1 <<  8)) printk(BIOS_DEBUG, "RI ");
 186         if (gpe0_sts & (1 <<  7)) printk(BIOS_DEBUG, "SMB_WAK ");
 187         if (gpe0_sts & (1 <<  6)) printk(BIOS_DEBUG, "TCO_SCI ");
 188         if (gpe0_sts & (1 <<  5)) printk(BIOS_DEBUG, "AC97 ");
 189         if (gpe0_sts & (1 <<  4)) printk(BIOS_DEBUG, "USB2 ");
 190         if (gpe0_sts & (1 <<  3)) printk(BIOS_DEBUG, "USB1 ");
 191         if (gpe0_sts & (1 <<  2)) printk(BIOS_DEBUG, "HOT_PLUG ");
 192         if (gpe0_sts & (1 <<  0)) printk(BIOS_DEBUG, "THRM ");
 193         printk(BIOS_DEBUG, "\n");
 194 }
 195
 196
 197 /**
 198  * @brief read and clear TCOx_STS
 199  * @return TCOx_STS registers
 200  */
 201 static u32 reset_tco_status(void)
 202 {
 203         u32 tcobase = pmbase + 0x60;
 204         u32 reg32;
 205
 206         reg32 = inl(tcobase + 0x04);
 207         /* set status bits are cleared by writing 1 to them */
 208         outl(reg32 & ~(1<<18), tcobase + 0x04); //  Don't clear BOOT_STS before SECOND_TO_STS
 209         if (reg32 & (1 << 18))
 210                 outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
 211
 212         return reg32;
 213 }
 214
 215
 216 static void dump_tco_status(u32 tco_sts)
 217 {
 218         printk(BIOS_DEBUG, "TCO_STS: ");
 219         if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
 220         if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
 221         if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
 222         if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
 223         if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
 224         if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
 225         if (tco_sts & (1 <<  9)) printk(BIOS_DEBUG, "DMISCI ");
 226         if (tco_sts & (1 <<  8)) printk(BIOS_DEBUG, "BIOSWR ");
 227         if (tco_sts & (1 <<  7)) printk(BIOS_DEBUG, "NEWCENTURY ");
 228         if (tco_sts & (1 <<  3)) printk(BIOS_DEBUG, "TIMEOUT ");
 229         if (tco_sts & (1 <<  2)) printk(BIOS_DEBUG, "TCO_INT ");
 230         if (tco_sts & (1 <<  1)) printk(BIOS_DEBUG, "SW_TCO ");
 231         if (tco_sts & (1 <<  0)) printk(BIOS_DEBUG, "NMI2SMI ");
 232         printk(BIOS_DEBUG, "\n");
 233 }
 234
 235 /* We are using PCIe accesses for now
 236  *  1. the chipset can do it
 237  *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
 238  */
 239 #include <arch/pci_mmio_cfg.h>
 240
 241 int southbridge_io_trap_handler(int smif)
 242 {
 243         switch (smif) {
 244         case 0x32:
 245                 printk(BIOS_DEBUG, "OS Init\n");
 246                 /* gnvs->smif:
 247                  *  On success, the IO Trap Handler returns 0
 248                  *  On failure, the IO Trap Handler returns a value != 0
 249                  */
 250                 gnvs->smif = 0;
 251                 return 1; /* IO trap handled */
 252         }
 253
 254         /* Not handled */
 255         return 0;
 256 }
 257
 258 /**
 259  * @brief Set the EOS bit
 260  */
 261 void southbridge_smi_set_eos(void)
 262 {
 263         u8 reg8;
 264
 265         reg8 = inb(pmbase + SMI_EN);
 266         reg8 |= EOS;
 267         outb(reg8, pmbase + SMI_EN);
 268 }
 269
 270 static void busmaster_disable_on_bus(int bus)
 271 {
 272         int slot, func;
 273         unsigned int val;
 274         unsigned char hdr;
 275
 276         for (slot = 0; slot < 0x20; slot++) {
 277                 for (func = 0; func < 8; func++) {
 278                         u32 reg32;
 279                         device_t dev = PCI_DEV(bus, slot, func);
 280
 281                         val = pci_read_config32(dev, PCI_VENDOR_ID);
 282
 283                         if (val == 0xffffffff || val == 0x00000000 ||
 284                             val == 0x0000ffff || val == 0xffff0000)
 285                                 continue;
 286
 287                         /* Disable Bus Mastering for this one device */
 288                         reg32 = pci_read_config32(dev, PCI_COMMAND);
 289                         reg32 &= ~PCI_COMMAND_MASTER;
 290                         pci_write_config32(dev, PCI_COMMAND, reg32);
 291
 292                         /* If this is a bridge, then follow it. */
 293                         hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
 294                         hdr &= 0x7f;
 295                         if (hdr == PCI_HEADER_TYPE_BRIDGE ||
 296                             hdr == PCI_HEADER_TYPE_CARDBUS) {
 297                                 unsigned int buses;
 298                                 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
 299                                 busmaster_disable_on_bus((buses >> 8) & 0xff);
 300                         }
 301                 }
 302         }
 303 }
 304
 305
 306 static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
 307 {
 308         u8 reg8;
 309         u32 reg32;
 310         u8 slp_typ;
 311         u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 312
 313         // save and recover RTC port values
 314         u8 tmp70, tmp72;
 315         tmp70 = inb(0x70);
 316         tmp72 = inb(0x72);
 317         get_option(&s5pwr, "power_on_after_fail");
 318         outb(tmp70, 0x70);
 319         outb(tmp72, 0x72);
 320
 321         /* First, disable further SMIs */
 322         reg8 = inb(pmbase + SMI_EN);
 323         reg8 &= ~SLP_SMI_EN;
 324         outb(reg8, pmbase + SMI_EN);
 325
 326         /* Figure out SLP_TYP */
 327         reg32 = inl(pmbase + PM1_CNT);
 328         printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
 329         slp_typ = (reg32 >> 10) & 7;
 330
 331         /* Next, do the deed.
 332          */
 333
 334         switch (slp_typ) {
 335         case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
 336         case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
 337         case 5:
 338                 printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
 339                 /* Invalidate the cache before going to S3 */
 340                 wbinvd();
 341                 break;
 342         case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
 343         case 7:
 344                 printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
 345
 346                 outl(0, pmbase + GPE0_EN);
 347
 348                 /* Always set the flag in case CMOS was changed on runtime. For
 349                  * "KEEP", switch to "OFF" - KEEP is software emulated
 350                  */
 351                 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
 352                 if (s5pwr == MAINBOARD_POWER_ON) {
 353                         reg8 &= ~1;
 354                 } else {
 355                         reg8 |= 1;
 356                 }
 357                 pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
 358
 359                 /* also iterates over all bridges on bus 0 */
 360                 busmaster_disable_on_bus(0);
 361                 break;
 362         default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
 363         }
 364
 365 #if !CONFIG_SMM_TSEG
 366         /* Unlock the SMI semaphore. We're currently in SMM, and the semaphore
 367          * will never be unlocked because the next outl will switch off the CPU.
 368          * This might open a small race between the smi_release_lock() and the outl()
 369          * for other SMI handlers. Not sure if this could cause trouble. */
 370          if (slp_typ == 5)
 371                 smi_release_lock();
 372 #endif
 373
 374         /* Write back to the SLP register to cause the originally intended
 375          * event again. We need to set BIT13 (SLP_EN) though to make the
 376          * sleep happen.
 377          */
 378         outl(reg32 | SLP_EN, pmbase + PM1_CNT);
 379
 380         /* Make sure to stop executing code here for S3/S4/S5 */
 381         if (slp_typ > 1)
 382                 halt();
 383         /* In most sleep states, the code flow of this function ends at
 384          * the line above. However, if we entered sleep state S1 and wake
 385          * up again, we will continue to execute code in this function.
 386          */
 387         reg32 = inl(pmbase + PM1_CNT);
 388         if (reg32 & SCI_EN) {
 389                 /* The OS is not an ACPI OS, so we set the state to S0 */
 390                 reg32 &= ~(SLP_EN | SLP_TYP);
 391                 outl(reg32, pmbase + PM1_CNT);
 392         }
 393 }
 394
 395 static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)
 396 {
 397         u32 pmctrl;
 398         u8 reg8;
 399
 400         /* Emulate B2 register as the FADT / Linux expects it */
 401
 402         reg8 = inb(APM_CNT);
 403         if (mainboard_smi_apmc(reg8))
 404                 return;
 405
 406         switch (reg8) {
 407         case APM_CNT_CST_CONTROL:
 408                 /* Calling this function seems to cause
 409                  * some kind of race condition in Linux
 410                  * and causes a kernel oops
 411                  */
 412                 printk(BIOS_DEBUG, "C-state control\n");
 413                 break;
 414         case APM_CNT_PST_CONTROL:
 415                 /* Calling this function seems to cause
 416                  * some kind of race condition in Linux
 417                  * and causes a kernel oops
 418                  */
 419                 printk(BIOS_DEBUG, "P-state control\n");
 420                 break;
 421         case APM_CNT_ACPI_DISABLE:
 422                 pmctrl = inl(pmbase + PM1_CNT);
 423                 pmctrl &= ~SCI_EN;
 424                 outl(pmctrl, pmbase + PM1_CNT);
 425                 printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
 426                 break;
 427         case APM_CNT_ACPI_ENABLE:
 428                 pmctrl = inl(pmbase + PM1_CNT);
 429                 pmctrl |= SCI_EN;
 430                 outl(pmctrl, pmbase + PM1_CNT);
 431                 printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 432                 break;
 433         case APM_CNT_GNVS_UPDATE:
 434                 if (smm_initialized) {
 435                         printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
 436                         return;
 437                 }
 438                 gnvs = *(global_nvs_t **)0x500;
 439                 smm_initialized = 1;
 440                 printk(BIOS_DEBUG, "SMI#: Setting up structures to %p\n", gnvs);
 441                 break;
 442         default:
 443                 printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8);
 444         }
 445 }
 446
 447 static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)
 448 {
 449         u16 pm1_sts;
 450         volatile u8 cmos_status;
 451
 452         pm1_sts = reset_pm1_status();
 453         dump_pm1_status(pm1_sts);
 454
 455         /* While OSPM is not active, poweroff immediately
 456          * on a power button event.
 457          */
 458         if (pm1_sts & PWRBTN_STS) {
 459                 // power button pressed
 460                 u32 reg32;
 461                 reg32 = (7 << 10) | (1 << 13);
 462                 outl(reg32, pmbase + PM1_CNT);
 463         }
 464
 465         if (pm1_sts & RTC_STS) {
 466                 /* read RTC status register to disable the interrupt */
 467                 cmos_status = cmos_read(RTC_REG_C);
 468                 printk(BIOS_DEBUG, "RTC IRQ status: %02X\n", cmos_status);
 469         }
 470 }
 471
 472 static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
 473 {
 474         u32 gpe0_sts;
 475
 476         gpe0_sts = reset_gpe0_status();
 477         dump_gpe0_status(gpe0_sts);
 478 }
 479
 480 static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
 481 {
 482         u16 reg16;
 483         reg16 = inw(pmbase + ALT_GP_SMI_STS);
 484         outw(reg16, pmbase + ALT_GP_SMI_STS);
 485
 486         reg16 &= inw(pmbase + ALT_GP_SMI_EN);
 487
 488         mainboard_smi_gpi(reg16);
 489
 490         if (reg16)
 491                 printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
 492 }
 493
 494 static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
 495 {
 496         u32 reg32;
 497
 498         reg32 = inl(pmbase + SMI_EN);
 499
 500         /* Are periodic SMIs enabled? */
 501         if ((reg32 & MCSMI_EN) == 0)
 502                 return;
 503
 504         printk(BIOS_DEBUG, "Microcontroller SMI.\n");
 505 }
 506
 507
 508
 509 static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)
 510 {
 511         u32 tco_sts;
 512
 513         tco_sts = reset_tco_status();
 514
 515         /* Any TCO event? */
 516         if (!tco_sts)
 517                 return;
 518
 519         if (tco_sts & (1 << 8)) { // BIOSWR
 520                 u8 bios_cntl;
 521
 522                 bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
 523
 524                 if (bios_cntl & 1) {
 525                         /* BWE is RW, so the SMI was caused by a
 526                          * write to BWE, not by a write to the BIOS
 527                          */
 528
 529                         /* This is the place where we notice someone
 530                          * is trying to tinker with the BIOS. We are
 531                          * trying to be nice and just ignore it. A more
 532                          * resolute answer would be to power down the
 533                          * box.
 534                          */
 535                         printk(BIOS_DEBUG, "Switching back to RO\n");
 536                         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
 537                 } /* No else for now? */
 538         } else if (tco_sts & (1 << 3)) { /* TIMEOUT */
 539                 /* Handle TCO timeout */
 540                 printk(BIOS_DEBUG, "TCO Timeout.\n");
 541         } else if (!tco_sts) {
 542                 dump_tco_status(tco_sts);
 543         }
 544 }
 545
 546 static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)
 547 {
 548         u32 reg32;
 549
 550         reg32 = inl(pmbase + SMI_EN);
 551
 552         /* Are periodic SMIs enabled? */
 553         if ((reg32 & PERIODIC_EN) == 0)
 554                 return;
 555
 556         printk(BIOS_DEBUG, "Periodic SMI.\n");
 557 }
 558
 559 static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
 560 {
 561 #define IOTRAP(x) (trap_sts & (1 << x))
 562         u32 trap_sts, trap_cycle;
 563         u32 data, mask = 0;
 564         int i;
 565
 566         trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
 567         RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
 568
 569         trap_cycle = RCBA32(0x1e10);
 570         for (i=16; i<20; i++) {
 571                 if (trap_cycle & (1 << i))
 572                         mask |= (0xff << ((i - 16) << 2));
 573         }
 574
 575
 576         /* IOTRAP(3) SMI function call */
 577         if (IOTRAP(3)) {
 578                 if (gnvs && gnvs->smif)
 579                         io_trap_handler(gnvs->smif); // call function smif
 580                 return;
 581         }
 582
 583         /* IOTRAP(2) currently unused
 584          * IOTRAP(1) currently unused */
 585
 586         /* IOTRAP(0) SMIC: currently unused  */
 587
 588         printk(BIOS_DEBUG, "  trapped io address = 0x%x\n", trap_cycle & 0xfffc);
 589         for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, "  TRAP = %d\n", i);
 590         printk(BIOS_DEBUG, "  AHBE = %x\n", (trap_cycle >> 16) & 0xf);
 591         printk(BIOS_DEBUG, "  MASK = 0x%08x\n", mask);
 592         printk(BIOS_DEBUG, "  read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
 593
 594         if (!(trap_cycle & (1 << 24))) {
 595                 /* Write Cycle */
 596                 data = RCBA32(0x1e18);
 597                 printk(BIOS_DEBUG, "  iotrap written data = 0x%08x\n", data);
 598         }
 599 #undef IOTRAP
 600 }
 601
 602 typedef void (*smi_handler_t)(unsigned int node,
 603                 smm_state_save_area_t *state_save);
 604
 605 smi_handler_t southbridge_smi[32] = {
 606         NULL,                     //  [0] reserved
 607         NULL,                     //  [1] reserved
 608         NULL,                     //  [2] BIOS_STS
 609         NULL,                     //  [3] LEGACY_USB_STS
 610         southbridge_smi_sleep,    //  [4] SLP_SMI_STS
 611         southbridge_smi_apmc,     //  [5] APM_STS
 612         NULL,                     //  [6] SWSMI_TMR_STS
 613         NULL,                     //  [7] reserved
 614         southbridge_smi_pm1,      //  [8] PM1_STS
 615         southbridge_smi_gpe0,     //  [9] GPE0_STS
 616         southbridge_smi_gpi,      // [10] GPI_STS
 617         southbridge_smi_mc,       // [11] MCSMI_STS
 618         NULL,                     // [12] DEVMON_STS
 619         southbridge_smi_tco,      // [13] TCO_STS
 620         southbridge_smi_periodic, // [14] PERIODIC_STS
 621         NULL,                     // [15] SERIRQ_SMI_STS
 622         NULL,                     // [16] SMBUS_SMI_STS
 623         NULL,                     // [17] LEGACY_USB2_STS
 624         NULL,                     // [18] INTEL_USB2_STS
 625         NULL,                     // [19] reserved
 626         NULL,                     // [20] PCI_EXP_SMI_STS
 627         southbridge_smi_monitor,  // [21] MONITOR_STS
 628         NULL,                     // [22] reserved
 629         NULL,                     // [23] reserved
 630         NULL,                     // [24] reserved
 631         NULL,                     // [25] EL_SMI_STS
 632         NULL,                     // [26] SPI_STS
 633         NULL,                     // [27] reserved
 634         NULL,                     // [28] reserved
 635         NULL,                     // [29] reserved
 636         NULL,                     // [30] reserved
 637         NULL                      // [31] reserved
 638 };
 639
 640 /**
 641  * @brief Interrupt handler for SMI#
 642  * @param node
 643  * @param state_save
 644  */
 645
 646 void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
 647 {
 648         int i, dump = 0;
 649         u32 smi_sts;
 650
 651         /* Update global variable pmbase */
 652         pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
 653
 654         /* We need to clear the SMI status registers, or we won't see what's
 655          * happening in the following calls.
 656          */
 657         smi_sts = reset_smi_status();
 658
 659         /* Filter all non-enabled SMI events */
 660         // FIXME Double check, this clears MONITOR
 661         // smi_sts &= inl(pmbase + SMI_EN);
 662
 663         /* Call SMI sub handler for each of the status bits */
 664         for (i = 0; i < 31; i++) {
 665                 if (smi_sts & (1 << i)) {
 666                         if (southbridge_smi[i])
 667                                 southbridge_smi[i](node, state_save);
 668                         else {
 669                                 printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
 670                                                 "handler available.\n", i);
 671                                 dump = 1;
 672                         }
 673                 }
 674         }
 675
 676         if(dump) {
 677                 dump_smi_status(smi_sts);
 678         }
 679
 680 }