src/southbridge/intel/i3100/pciexp_portb.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Arastra, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 /* This code is based on src/northbridge/intel/e7520/pciexp_porta.c */
  18
  19 #include <console/console.h>
  20 #include <device/device.h>
  21 #include <device/pci.h>
  22 #include <device/pci_ids.h>
  23 #include <device/pci_ops.h>
  24 #include <device/pciexp.h>
  25 #include <arch/io.h>
  26 #include "chip.h"
  27 #include <reset.h>
  28
  29 #define PCIE_LCTL 0x50
  30 #define PCIE_LSTS 0x52
  31
  32 typedef struct northbridge_intel_i3100_config config_t;
  33
  34 static void pcie_init(struct device *dev)
  35 {
  36 }
  37
  38 static void pcie_scan_bridge(struct device *dev)
  39 {
  40         u16 val;
  41         u16 ctl;
  42         int flag = 0;
  43         do {
  44                 val = pci_read_config16(dev, PCIE_LSTS);
  45                 printk(BIOS_DEBUG, "pcie portb link status: %02x\n", val);
  46                 if ((val & (1<<10)) && (!flag)) { /* training error */
  47                         ctl = pci_read_config16(dev, PCIE_LCTL);
  48                         pci_write_config16(dev, PCIE_LCTL, (ctl | (1<<5)));
  49                         val = pci_read_config16(dev, PCIE_LSTS);
  50                         printk(BIOS_DEBUG, "pcie portb reset link status: %02x\n", val);
  51                         flag=1;
  52                         hard_reset();
  53                 }
  54         } while (val & (3<<10));
  55
  56         pciexp_scan_bridge(dev);
  57 }
  58
  59 static struct device_operations pcie_ops  = {
  60         .read_resources   = pci_bus_read_resources,
  61         .set_resources    = pci_dev_set_resources,
  62         .enable_resources = pci_bus_enable_resources,
  63         .init             = pcie_init,
  64         .scan_bus         = pcie_scan_bridge,
  65         .reset_bus        = pci_bus_reset,
  66         .ops_pci          = 0,
  67 };
  68
  69 static const struct pci_driver pci_driver_0 __pci_driver = {
  70         .ops    = &pcie_ops,
  71         .vendor = PCI_VENDOR_ID_INTEL,
  72         .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB0,
  73 };
  74
  75 static const struct pci_driver pci_driver_1 __pci_driver = {
  76         .ops    = &pcie_ops,
  77         .vendor = PCI_VENDOR_ID_INTEL,
  78         .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB1,
  79 };
  80
  81 static const struct pci_driver pci_driver_2 __pci_driver = {
  82         .ops    = &pcie_ops,
  83         .vendor = PCI_VENDOR_ID_INTEL,
  84         .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB2,
  85 };
  86
  87 static const struct pci_driver pci_driver_3 __pci_driver = {
  88         .ops    = &pcie_ops,
  89         .vendor = PCI_VENDOR_ID_INTEL,
  90         .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB3,
  91 };