src/southbridge/intel/i3100/chip.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Arastra, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 struct southbridge_intel_i3100_config
  18 {
  19 #define I3100_GPIO_USE_MASK      0x03
  20 #define I3100_GPIO_USE_DEFAULT   0x00
  21 #define I3100_GPIO_USE_AS_NATIVE 0x01
  22 #define I3100_GPIO_USE_AS_GPIO   0x02
  23
  24 #define I3100_GPIO_SEL_MASK      0x0c
  25 #define I3100_GPIO_SEL_DEFAULT   0x00
  26 #define I3100_GPIO_SEL_OUTPUT    0x04
  27 #define I3100_GPIO_SEL_INPUT     0x08
  28
  29 #define I3100_GPIO_LVL_MASK      0x30
  30 #define I3100_GPIO_LVL_DEFAULT   0x00
  31 #define I3100_GPIO_LVL_LOW       0x10
  32 #define I3100_GPIO_LVL_HIGH      0x20
  33 #define I3100_GPIO_LVL_BLINK     0x30
  34
  35 #define I3100_GPIO_INV_MASK      0xc0
  36 #define I3100_GPIO_INV_DEFAULT   0x00
  37 #define I3100_GPIO_INV_OFF       0x40
  38 #define I3100_GPIO_INV_ON        0x80
  39
  40         /* GPIO use select */
  41         u8 gpio[64];
  42         int sata_ports_implemented;
  43         u32 pirq_a_d;
  44         u32 pirq_e_h;
  45 };