src/southbridge/intel/fsp_rangeley/watchdog.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright (C) 2011 Google Inc.
   6  * Copyright (C) 2013 Sage Electronic Engineering, LLC.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; version 2 of
  11  * the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <console/console.h>
  20 #include <arch/io.h>
  21 #include <device/device.h>
  22 #include <device/pci.h>
  23 #include <watchdog.h>
  24 #include "soc.h"
  25
  26 void watchdog_off(void)
  27 {
  28         device_t dev;
  29         u32 value, abase;
  30
  31         /* Turn off the watchdog. */
  32         dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
  33
  34         /* Enable I/O space. */
  35         value = pci_read_config16(dev, 0x04);
  36         value |= 1;
  37         pci_write_config16(dev, 0x04, value);
  38
  39         /* Get TCO base. */
  40         abase = (pci_read_config32(dev, ABASE) & ~0xf);
  41
  42         /* Disable the watchdog timer. */
  43         value = inw(abase + 0x68);
  44         value |= 1 << 11;
  45         outw(value, abase + 0x68);
  46
  47         /* Clear TCO timeout status. */
  48         outw(0x0008, abase + 0x64);
  49         outw(0x0002, abase + 0x66);
  50
  51         printk(BIOS_DEBUG, "TCO Watchdog disabled\n");
  52 }