2 * Copyright (c) 2011 The Chromium OS Authors.
3 * Copyright (C) 2013, Intel Corporation.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but without any warranty; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 /* This file is derived from the flashrom project. */
22 #include <console/console.h>
23 #include <device/pci_ids.h>
25 #include <spi-generic.h>
27 static int ich_status_poll(u16 bitmask
, int wait_til_set
);
30 #include <arch/pci_mmio_cfg.h>
31 #define pci_read_config_byte(dev, reg, targ)\
32 *(targ) = pci_read_config8(dev, reg)
33 #define pci_read_config_word(dev, reg, targ)\
34 *(targ) = pci_read_config16(dev, reg)
35 #define pci_read_config_dword(dev, reg, targ)\
36 *(targ) = pci_read_config32(dev, reg)
37 #define pci_write_config_byte(dev, reg, val)\
38 pci_write_config8(dev, reg, val)
39 #define pci_write_config_word(dev, reg, val)\
40 pci_write_config16(dev, reg, val)
41 #define pci_write_config_dword(dev, reg, val)\
42 pci_write_config32(dev, reg, val)
44 #include <device/device.h>
45 #include <device/pci.h>
46 #define pci_read_config_byte(dev, reg, targ)\
47 *(targ) = pci_read_config8(dev, reg)
48 #define pci_read_config_word(dev, reg, targ)\
49 *(targ) = pci_read_config16(dev, reg)
50 #define pci_read_config_dword(dev, reg, targ)\
51 *(targ) = pci_read_config32(dev, reg)
52 #define pci_write_config_byte(dev, reg, val)\
53 pci_write_config8(dev, reg, val)
54 #define pci_write_config_word(dev, reg, val)\
55 pci_write_config16(dev, reg, val)
56 #define pci_write_config_dword(dev, reg, val)\
57 pci_write_config32(dev, reg, val)
60 typedef struct spi_slave ich_spi_slave
;
62 static int ichspi_lock
= 0;
64 typedef struct ich7_spi_regs
{
74 } __attribute__((packed
)) ich7_spi_regs
;
76 typedef struct ich9_spi_regs
{
81 uint32_t _reserved0
; // 0xC
82 uint32_t fdata
[16]; // 0x10
83 uint32_t frap
; // 0x50
84 uint32_t freg
[5]; // 0x54
85 uint32_t _reserved1
[3]; // 0x67
86 uint32_t pr
[5]; // 0x74
87 uint32_t _reserved2
[2]; // 0x88
89 uint8_t ssfc
[3]; // 0x91
90 uint16_t preop
; // 0x94
91 uint16_t optype
; // 0x96
92 uint8_t opmenu
[8]; // 0x98
93 uint32_t bbar
; // 0xB0
94 uint8_t _reserved3
[12];
97 uint8_t _reserved4
[8];
101 uint8_t _reserved5
[4];
103 uint8_t _reserved6
[28];
107 } __attribute__((packed
)) ich9_spi_regs
;
109 typedef struct ich10_spi_regs
{
118 uint32_t _reserved1
[3];
120 uint32_t _reserved2
[2];
126 uint8_t _reserved3
[16];
129 uint8_t _reserved4
[8];
133 uint8_t _reserved5
[4];
135 uint8_t _reserved6
[36];
139 } __attribute__((packed
)) ich10_spi_regs
;
141 typedef struct ich_spi_controller
{
155 } ich_spi_controller
;
157 static ich_spi_controller cntlr
;
166 SPIS_RESERVED_MASK
= 0x7ff0,
167 SSFS_RESERVED_MASK
= 0x7fe2
171 SPIC_SCGO
= 0x000002,
173 SPIC_SPOP
= 0x000008,
177 SSFC_SCF_MASK
= 0x070000,
178 SSFC_RESERVED
= 0xf80000
185 HSFS_BERASE_MASK
= 0x0018,
186 HSFS_BERASE_SHIFT
= 3,
188 HSFS_FDOPSS
= 0x2000,
190 HSFS_FLOCKDN
= 0x8000
195 HSFC_FCYCLE_MASK
= 0x0006,
196 HSFC_FCYCLE_SHIFT
= 1,
197 HSFC_FDBC_MASK
= 0x3f00,
205 BCR_SRC_MASK
= 0x000c,
206 BCR_SRC_SHIFT
= 0x0002,
207 BCR_SRC_NO_PREF
= 0x0000,
208 BCR_SRC_NO_PREF_CACHE
= 0x0004,
209 BCR_SRC_EN_PREF_CACHE
= 0x0008,
212 BCR_RESERVED_MASK
= 0xffc0
216 SPI_OPCODE_TYPE_READ_NO_ADDRESS
= 0,
217 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
= 1,
218 SPI_OPCODE_TYPE_READ_WITH_ADDRESS
= 2,
219 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
= 3,
222 #if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
224 static u8
readb_(const void *addr
)
227 printk(BIOS_DEBUG
, "read %2.2x from %4.4x\n",
228 v
, ((unsigned) addr
& 0xffff) - 0xf020);
232 static u16
readw_(const void *addr
)
234 u16 v
= read16(addr
);
235 printk(BIOS_DEBUG
, "read %4.4x from %4.4x\n",
236 v
, ((unsigned) addr
& 0xffff) - 0xf020);
240 static u32
readl_(const void *addr
)
242 u32 v
= read32(addr
);
243 printk(BIOS_DEBUG
, "read %8.8x from %4.4x\n",
244 v
, ((unsigned) addr
& 0xffff) - 0xf020);
248 static void writeb_(u8 b
, const void *addr
)
251 printk(BIOS_DEBUG
, "wrote %2.2x to %4.4x\n",
252 b
, ((unsigned) addr
& 0xffff) - 0xf020);
255 static void writew_(u16 b
, const void *addr
)
258 printk(BIOS_DEBUG
, "wrote %4.4x to %4.4x\n",
259 b
, ((unsigned) addr
& 0xffff) - 0xf020);
262 static void writel_(u32 b
, const void *addr
)
264 write32((unsigned long)addr
, b
);
265 printk(BIOS_DEBUG
, "wrote %8.8x to %4.4x\n",
266 b
, ((unsigned) addr
& 0xffff) - 0xf020);
269 #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
271 #define readb_(a) read8(a)
272 #define readw_(a) read16(a)
273 #define readl_(a) read32(a)
274 #define writeb_(val, addr) write8(addr, val)
275 #define writew_(val, addr) write16(addr, val)
276 #define writel_(val, addr) write32(addr, val)
278 #endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
280 static void write_reg(const void *value
, void *dest
, uint32_t size
)
282 const uint8_t *bvalue
= value
;
283 uint8_t *bdest
= dest
;
286 writel_(*(const uint32_t *)bvalue
, bdest
);
287 bdest
+= 4; bvalue
+= 4; size
-= 4;
290 writeb_(*bvalue
, bdest
);
291 bdest
++; bvalue
++; size
--;
295 static void read_reg(const void *src
, void *value
, uint32_t size
)
297 const uint8_t *bsrc
= src
;
298 uint8_t *bvalue
= value
;
301 *(uint32_t *)bvalue
= readl_(bsrc
);
302 bsrc
+= 4; bvalue
+= 4; size
-= 4;
305 *bvalue
= readb_(bsrc
);
306 bsrc
++; bvalue
++; size
--;
310 static void ich_set_bbar(uint32_t minaddr
)
312 const uint32_t bbar_mask
= 0x00ffff00;
313 uint32_t ichspi_bbar
;
315 if (cntlr
.bbar
== NULL
)
318 minaddr
&= bbar_mask
;
319 ichspi_bbar
= readl_(cntlr
.bbar
) & ~bbar_mask
;
320 ichspi_bbar
|= minaddr
;
321 writel_(ichspi_bbar
, cntlr
.bbar
);
324 struct spi_slave
*spi_setup_slave(unsigned int bus
, unsigned int cs
)
326 ich_spi_slave
*slave
= malloc(sizeof(*slave
));
329 printk(BIOS_DEBUG
, "ICH SPI: Bad allocation\n");
333 memset(slave
, 0, sizeof(*slave
));
341 * Check if this device ID matches one of supported Intel SOC devices.
343 * Return the ICH version if there is a match, or zero otherwise.
345 static inline int get_ich_version(uint16_t device_id
)
348 if ((device_id
>= PCI_DEVICE_ID_INTEL_RANGELEY_LPC_MIN
&&
349 device_id
<= PCI_DEVICE_ID_INTEL_RANGELEY_LPC_MAX
))
361 uint16_t vendor_id
, device_id
;
364 dev
= PCI_DEV(0, 31, 0);
366 dev
= dev_find_slot(0, PCI_DEVFN(31, 0));
368 pci_read_config_dword(dev
, 0, &ids
);
370 device_id
= (ids
>> 16);
372 if (vendor_id
!= PCI_VENDOR_ID_INTEL
) {
373 printk(BIOS_DEBUG
, "SPI: No SOC found.\n");
377 ich_version
= get_ich_version(device_id
);
380 printk(BIOS_DEBUG
, "SPI: No known SOC found.\n");
384 switch (ich_version
) {
387 uint8_t *spibase
; /* SPI Base Address */
388 uint32_t sbase
; /* SPI Base Address Register */
389 pci_read_config_dword(dev
, 0x54, &sbase
);
390 /* Bits 31-9 are the base address, 8-4 are reserved, 3-0 are used. */
391 spibase
= (uint8_t *)(sbase
& 0xffffff00);
392 ich10_spi_regs
*ich10_spi
=
393 (ich10_spi_regs
*)(spibase
);
394 ichspi_lock
= readw_(&ich10_spi
->hsfs
) & HSFS_FLOCKDN
;
395 cntlr
.opmenu
= ich10_spi
->opmenu
;
396 cntlr
.menubytes
= sizeof(ich10_spi
->opmenu
);
397 cntlr
.optype
= &ich10_spi
->optype
;
398 cntlr
.addr
= &ich10_spi
->faddr
;
399 cntlr
.data
= (uint8_t *)ich10_spi
->fdata
;
400 cntlr
.databytes
= sizeof(ich10_spi
->fdata
);
401 cntlr
.status
= &ich10_spi
->ssfs
;
402 cntlr
.control
= (uint16_t *)ich10_spi
->ssfc
;
404 cntlr
.preop
= &ich10_spi
->preop
;
405 cntlr
.bcr
= (uint8_t *)&ich10_spi
->bcr
;
409 printk(BIOS_DEBUG
, "ICH SPI: Unrecognized ICH version %d.\n", ich_version
);
414 /* Disable the BIOS write protect so write commands are allowed. */
415 switch (ich_version
) {
418 /* Deassert SMM BIOS write protect(SMM BWP) and assert enable flash write(BIOSWE) */
419 bios_cntl
= readb_(cntlr
.bcr
);
420 bios_cntl
&= ~BCR_SMMBWP
;
421 bios_cntl
|= BCR_BIOSWE
;
422 writeb_(bios_cntl
, cntlr
.bcr
);
431 int spi_claim_bus(struct spi_slave
*slave
)
433 /* Handled by ICH automatically. */
437 void spi_release_bus(struct spi_slave
*slave
)
439 /* Handled by ICH automatically. */
442 typedef struct spi_transaction
{
452 static inline void spi_use_out(spi_transaction
*trans
, unsigned bytes
)
455 trans
->bytesout
-= bytes
;
458 static inline void spi_use_in(spi_transaction
*trans
, unsigned bytes
)
461 trans
->bytesin
-= bytes
;
464 static void spi_setup_type(spi_transaction
*trans
)
468 /* Try to guess spi type from read/write sizes. */
469 if (trans
->bytesin
== 0) {
470 if (trans
->bytesout
> 4)
472 * If bytesin = 0 and bytesout > 4, we presume this is
473 * a write data operation, which is accompanied by an
476 trans
->type
= SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
;
478 trans
->type
= SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
;
482 if (trans
->bytesout
== 1) { /* and bytesin is > 0 */
483 trans
->type
= SPI_OPCODE_TYPE_READ_NO_ADDRESS
;
487 if (trans
->bytesout
== 4) { /* and bytesin is > 0 */
488 trans
->type
= SPI_OPCODE_TYPE_READ_WITH_ADDRESS
;
491 /* Fast read command is called with 5 bytes instead of 4 */
492 if (trans
->out
[0] == SPI_OPCODE_FAST_READ
&& trans
->bytesout
== 5) {
493 trans
->type
= SPI_OPCODE_TYPE_READ_WITH_ADDRESS
;
498 static int spi_setup_opcode(spi_transaction
*trans
)
501 uint8_t opmenu
[cntlr
.menubytes
];
503 trans
->opcode
= trans
->out
[0];
504 spi_use_out(trans
, 1);
506 /* The lock is off, so just use index 0. */
507 writeb_(trans
->opcode
, cntlr
.opmenu
);
508 optypes
= readw_(cntlr
.optype
);
509 optypes
= (optypes
& 0xfffc) | (trans
->type
& 0x3);
510 writew_(optypes
, cntlr
.optype
);
513 /* The lock is on. See if what we need is on the menu. */
515 uint16_t opcode_index
;
517 /* Write Enable is handled as atomic prefix */
518 if (trans
->opcode
== SPI_OPCODE_WREN
)
521 read_reg(cntlr
.opmenu
, opmenu
, sizeof(opmenu
));
522 for (opcode_index
= 0; opcode_index
< cntlr
.menubytes
;
524 if (opmenu
[opcode_index
] == trans
->opcode
)
528 if (opcode_index
== cntlr
.menubytes
) {
529 printk(BIOS_DEBUG
, "ICH SPI: Opcode %x not found\n",
534 optypes
= readw_(cntlr
.optype
);
535 optype
= (optypes
>> (opcode_index
* 2)) & 0x3;
536 if (trans
->type
== SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
&&
537 optype
== SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
&&
538 trans
->bytesout
>= 3) {
539 /* We guessed wrong earlier. Fix it up. */
540 trans
->type
= optype
;
542 if (optype
!= trans
->type
) {
543 printk(BIOS_DEBUG
, "ICH SPI: Transaction doesn't fit type %d\n",
551 static int spi_setup_offset(spi_transaction
*trans
)
553 /* Separate the SPI address and data. */
554 switch (trans
->type
) {
555 case SPI_OPCODE_TYPE_READ_NO_ADDRESS
:
556 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
:
558 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS
:
559 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
:
560 trans
->offset
= ((uint32_t)trans
->out
[0] << 16) |
561 ((uint32_t)trans
->out
[1] << 8) |
562 ((uint32_t)trans
->out
[2] << 0);
563 spi_use_out(trans
, 3);
566 printk(BIOS_DEBUG
, "Unrecognized SPI transaction type %#x\n", trans
->type
);
572 * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set
573 * below is True) or 0. In case the wait was for the bit(s) to set - write
574 * those bits back, which would cause resetting them.
576 * Return the last read status value on success or -1 on failure.
578 static int ich_status_poll(u16 bitmask
, int wait_til_set
)
580 int timeout
= 60000; /* This will result in 600 ms */
584 status
= readw_(cntlr
.status
);
585 if (wait_til_set
^ ((status
& bitmask
) == 0)) {
587 writew_((status
& bitmask
), cntlr
.status
);
593 printk(BIOS_DEBUG
, "ICH SPI: SCIP timeout, read %x, expected %x\n",
598 unsigned int spi_crop_chunk(unsigned int cmd_len
, unsigned int buf_len
)
600 return min(cntlr
.databytes
, buf_len
);
603 int spi_xfer(struct spi_slave
*slave
, const void *dout
,
604 unsigned int bytesout
, void *din
, unsigned int bytesin
)
607 int16_t opcode_index
;
611 spi_transaction trans
= {
617 /* There has to always at least be an opcode. */
618 if (!bytesout
|| !dout
) {
619 printk(BIOS_DEBUG
, "ICH SPI: No opcode for transfer\n");
622 /* Make sure if we read something we have a place to put it. */
623 if (bytesin
!= 0 && !din
) {
624 printk(BIOS_DEBUG
, "ICH SPI: Read but no target buffer\n");
628 if (ich_status_poll(SPIS_SCIP
, 0) == -1)
631 writew_(SPIS_CDS
| SPIS_FCERR
, cntlr
.status
);
633 spi_setup_type(&trans
);
634 if ((opcode_index
= spi_setup_opcode(&trans
)) < 0)
636 if ((with_address
= spi_setup_offset(&trans
)) < 0)
639 if (!ichspi_lock
&& trans
.opcode
== SPI_OPCODE_WREN
) {
641 * Treat Write Enable as Atomic Pre-Op if possible
642 * in order to prevent the Management Engine from
643 * issuing a transaction between WREN and DATA.
645 writew_(trans
.opcode
, cntlr
.preop
);
649 /* Preset control fields */
650 control
= SPIC_SCGO
| ((opcode_index
& 0x07) << 4);
652 /* Issue atomic preop cycle if needed */
653 if (readw_(cntlr
.preop
))
656 if (!trans
.bytesout
&& !trans
.bytesin
) {
657 /* SPI addresses are 24 bit only */
659 writel_(trans
.offset
& 0x00FFFFFF, cntlr
.addr
);
662 * This is a 'no data' command (like Write Enable), its
663 * bitesout size was 1, decremented to zero while executing
664 * spi_setup_opcode() above. Tell the chip to send the
667 writew_(control
, cntlr
.control
);
669 /* wait for the result */
670 status
= ich_status_poll(SPIS_CDS
| SPIS_FCERR
, 1);
674 if (status
& SPIS_FCERR
) {
675 printk(BIOS_DEBUG
, "ICH SPI: Command transaction error\n");
683 * Check if this is a write command attempting to transfer more bytes
684 * than the controller can handle. Iterations for writes are not
685 * supported here because each SPI write command needs to be preceded
686 * and followed by other SPI commands, and this sequence is controlled
687 * by the SPI chip driver.
689 if (trans
.bytesout
> cntlr
.databytes
) {
690 printk(BIOS_DEBUG
, "ICH SPI: Too much to write. Does your SPI chip driver use"
691 " spi_crop_chunk()?\n");
696 * Read or write up to databytes bytes at a time until everything has
699 while (trans
.bytesout
|| trans
.bytesin
) {
700 uint32_t data_length
;
702 /* SPI addresses are 24 bit only */
703 writel_(trans
.offset
& 0x00FFFFFF, cntlr
.addr
);
706 data_length
= min(trans
.bytesout
, cntlr
.databytes
);
708 data_length
= min(trans
.bytesin
, cntlr
.databytes
);
710 /* Program data into FDATA0 to N */
711 if (trans
.bytesout
) {
712 write_reg(trans
.out
, cntlr
.data
, data_length
);
713 spi_use_out(&trans
, data_length
);
715 trans
.offset
+= data_length
;
718 /* Add proper control fields' values */
719 control
&= ~((cntlr
.databytes
- 1) << 8);
721 control
|= (data_length
- 1) << 8;
724 writew_(control
, cntlr
.control
);
726 /* Wait for Cycle Done Status or Flash Cycle Error. */
727 status
= ich_status_poll(SPIS_CDS
| SPIS_FCERR
, 1);
731 if (status
& SPIS_FCERR
) {
732 printk(BIOS_DEBUG
, "ICH SPI: Data transaction error\n");
737 read_reg(cntlr
.data
, trans
.in
, data_length
);
738 spi_use_in(&trans
, data_length
);
740 trans
.offset
+= data_length
;
745 /* Clear atomic preop now that xfer is done */
746 writew_(0, cntlr
.preop
);