src/southbridge/intel/fsp_rangeley/chip.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright (C) 2014 Sage Electronic Engineering, LLC.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H
  18 #define SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H
  19
  20 #include <arch/acpi.h>
  21
  22 struct southbridge_intel_fsp_rangeley_config {
  23
  24         /**
  25          * GPI Routing configuration
  26          *
  27          * Only the lower two bits have a meaning:
  28          * 00: No effect
  29          * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
  30          * 10: SCI (if corresponding GPIO_EN bit is also set)
  31          * 11: reserved
  32          */
  33         uint8_t gpi0_routing;
  34         uint8_t gpi1_routing;
  35         uint8_t gpi2_routing;
  36         uint8_t gpi3_routing;
  37         uint8_t gpi4_routing;
  38         uint8_t gpi5_routing;
  39         uint8_t gpi6_routing;
  40         uint8_t gpi7_routing;
  41         uint8_t gpi8_routing;
  42         uint8_t gpi9_routing;
  43         uint8_t gpi10_routing;
  44         uint8_t gpi11_routing;
  45         uint8_t gpi12_routing;
  46         uint8_t gpi13_routing;
  47         uint8_t gpi14_routing;
  48         uint8_t gpi15_routing;
  49
  50         uint32_t gpe0_en;
  51         uint16_t alt_gp_smi_en;
  52
  53         /* IDE configuration */
  54         uint32_t ide_legacy_combined;
  55         uint32_t sata_ahci;
  56         uint8_t sata_port_map;
  57         uint32_t sata_port0_gen3_tx;
  58         uint32_t sata_port1_gen3_tx;
  59
  60         uint32_t gen1_dec;
  61         uint32_t gen2_dec;
  62         uint32_t gen3_dec;
  63         uint32_t gen4_dec;
  64
  65         /* Enable linear PCIe Root Port function numbers starting at zero */
  66         uint8_t pcie_port_coalesce;
  67
  68         /* Override PCIe ASPM */
  69         uint8_t pcie_aspm_f0;
  70         uint8_t pcie_aspm_f1;
  71         uint8_t pcie_aspm_f2;
  72         uint8_t pcie_aspm_f3;
  73         uint8_t pcie_aspm_f4;
  74         uint8_t pcie_aspm_f5;
  75         uint8_t pcie_aspm_f6;
  76         uint8_t pcie_aspm_f7;
  77
  78         /* ACPI configuration */
  79         uint8_t  fadt_pm_profile;
  80         uint16_t fadt_boot_arch;
  81
  82 };
  83
  84 #endif                          /* SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H */