2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2011 Google Inc.
5 ## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; version 2 of the License.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
17 config HAVE_INTEL_FIRMWARE
20 Chipset uses the Intel Firmware Descriptor to describe the
21 layout of the SPI ROM chip.
23 if HAVE_INTEL_FIRMWARE
25 comment "Intel Firmware"
28 bool "Add Intel descriptor.bin file"
33 string "Path and filename of the descriptor.bin file"
34 default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
35 depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD
38 bool "Add Intel ME/TXE firmware"
39 depends on HAVE_IFD_BIN
41 The Intel processor in the selected system requires a special firmware
42 for an integrated controller. This might be called the Management
43 Engine (ME), the Trusted Execution Engine (TXE) or something else
44 depending on the chip. This firmware might or might not be available
45 in coreboot's 3rdparty/blobs repository. If it is not and if you don't
46 have access to the firmware from elsewhere, you can still build
47 coreboot without it. In this case however, you'll have to make sure
48 that you don't overwrite your ME/TXE firmware on your flash ROM.
51 string "Path to management engine firmware"
52 default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
53 depends on HAVE_ME_BIN
56 bool "Add gigabit ethernet firmware"
57 depends on HAVE_IFD_BIN
59 The integrated gigabit ethernet controller needs a firmware file.
60 Select this if you are going to use the PCH integrated controller
61 and have the firmware.
64 string "Path to gigabit ethernet firmware"
65 depends on HAVE_GBE_BIN
66 default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin"
70 config BUILD_WITH_FAKE_IFD
71 bool "Build with a fake IFD" if !HAVE_IFD_BIN
73 If you don't have an Intel Firmware Descriptor (descriptor.bin) for your
74 board, you can select this option and coreboot will build without it.
75 The resulting coreboot.rom will not contain all parts required
76 to get coreboot running on your board. You can however write only the
77 BIOS section to your board's flash ROM and keep the other sections
78 untouched. Unfortunately the current version of flashrom doesn't
79 support this yet. But there is a patch pending [1].
81 WARNING: Never write a complete coreboot.rom to your flash ROM if it
82 was built with a fake IFD. It just won't work.
84 [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
86 config IFD_BIOS_SECTION
87 depends on BUILD_WITH_FAKE_IFD
88 string "BIOS Region Starting:Ending addresses within the ROM"
91 The BIOS region is typically the size of the CBFS area, and is located
92 at the end of the ROM space.
94 For an 8MB ROM with a 3MB CBFS area, this would look like:
98 depends on BUILD_WITH_FAKE_IFD
99 string "ME/TXE Region Starting:Ending addresses within the ROM"
102 The ME/TXE region typically starts at around 0x1000 and often fills the
103 ROM space not used by CBFS.
105 For an 8MB ROM with a 3MB CBFS area, this might look like:
106 0x00001000:0x004fffff
108 config IFD_GBE_SECTION
109 depends on BUILD_WITH_FAKE_IFD
110 string "GBE Region Starting:Ending addresses within the ROM"
113 The Gigabit Ethernet ROM region is used when an Intel NIC is built into
114 the Southbridge/SOC and the platform uses this device instead of an external
115 PCIe NIC. It will be located between the ME/TXE and the BIOS region.
117 Leave this empty if you're unsure.
119 config IFD_PLATFORM_SECTION
120 depends on BUILD_WITH_FAKE_IFD
121 string "Platform Region Starting:Ending addresses within the Rom"
124 The Platform region is used for platform specific data.
125 It will be located between the ME/TXE and the BIOS region.
127 Leave this empty if you're unsure.
129 config LOCK_MANAGEMENT_ENGINE
130 bool "Lock ME/TXE section"
131 depends on HAVE_ME_BIN
134 The Intel Firmware Descriptor supports preventing write accesses
135 from the host to the ME or TXE section in the firmware
136 descriptor. If the section is locked, it can only be overwritten
137 with an external SPI flash programmer. You will want this if you
138 want to increase security of your ROM image once you are sure
139 that the ME/TXE firmware is no longer going to change.
143 endif #INTEL_FIRMWARE