src/southbridge/intel/bd82x6x/usb_ehci.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <kconfig.h>
  18 #include <console/console.h>
  19 #include <device/device.h>
  20 #include <device/pci.h>
  21 #include <device/pci_ids.h>
  22 #include "pch.h"
  23 #include <device/pci_ehci.h>
  24 #include <arch/io.h>
  25
  26 static void usb_ehci_init(struct device *dev)
  27 {
  28         u32 reg32;
  29
  30         /* Disable Wake on Disconnect in RMH */
  31         reg32 = RCBA32(0x35b0);
  32         reg32 |= 0x22;
  33         RCBA32(0x35b0) = reg32;
  34
  35         printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
  36
  37         /* For others, done in MRC.  */
  38 #if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)
  39         pci_write_config32(dev, 0x84, 0x930c8811);
  40         pci_write_config32(dev, 0x88, 0x24000d30);
  41         pci_write_config32(dev, 0xf4, 0x80408588);
  42         pci_write_config32(dev, 0xf4, 0x80808588);
  43         pci_write_config32(dev, 0xf4, 0x00808588);
  44         pci_write_config32(dev, 0xfc, 0x205b1708);
  45 #endif
  46
  47         reg32 = pci_read_config32(dev, PCI_COMMAND);
  48         reg32 |= PCI_COMMAND_MASTER;
  49         //reg32 |= PCI_COMMAND_SERR;
  50         pci_write_config32(dev, PCI_COMMAND, reg32);
  51
  52         /* For others, done in MRC.  */
  53 #if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)
  54         struct resource *res;
  55         u8 access_cntl;
  56
  57         access_cntl = pci_read_config8(dev, 0x80);
  58
  59         /* Enable writes to protected registers. */
  60         pci_write_config8(dev, 0x80, access_cntl | 1);
  61
  62         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  63         if (res) {
  64                 /* Number of ports and companion controllers.  */
  65                 reg32 = read32((void *)(uintptr_t)(res->base + 4));
  66                 write32((void *)(uintptr_t)(res->base + 4),
  67                         (reg32 & 0xfff00000) | 3);
  68         }
  69
  70         /* Restore protection. */
  71         pci_write_config8(dev, 0x80, access_cntl);
  72 #endif
  73
  74         printk(BIOS_DEBUG, "done.\n");
  75 }
  76
  77 static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
  78 {
  79         u8 access_cntl;
  80
  81         access_cntl = pci_read_config8(dev, 0x80);
  82
  83         /* Enable writes to protected registers. */
  84         pci_write_config8(dev, 0x80, access_cntl | 1);
  85
  86         if (!vendor || !device) {
  87                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
  88                                 pci_read_config32(dev, PCI_VENDOR_ID));
  89         } else {
  90                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
  91                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
  92         }
  93
  94         /* Restore protection. */
  95         pci_write_config8(dev, 0x80, access_cntl);
  96 }
  97
  98 static struct pci_operations lops_pci = {
  99         .set_subsystem  = &usb_ehci_set_subsystem,
 100 };
 101
 102 static struct device_operations usb_ehci_ops = {
 103         .read_resources         = pci_ehci_read_resources,
 104         .set_resources          = pci_dev_set_resources,
 105         .enable_resources       = pci_dev_enable_resources,
 106         .init                   = usb_ehci_init,
 107         .scan_bus               = 0,
 108         .ops_pci                = &lops_pci,
 109 };
 110
 111 static const unsigned short pci_device_ids[] = { 0x1c26, 0x1c2d, 0x1e26, 0x1e2d,
 112                                                  0 };
 113
 114 static const struct pci_driver pch_usb_ehci __pci_driver = {
 115         .ops     = &usb_ehci_ops,
 116         .vendor  = PCI_VENDOR_ID_INTEL,
 117         .devices = pci_device_ids,
 118 };